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| author | Tim Newsome <tim@sifive.com> | 2018-12-04 13:46:35 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-12-13 12:52:03 -0800 |
| commit | 5c1849722546813bae3fe6002ce8961dfd14f2f1 (patch) | |
| tree | f80f549a647ae59c405120949d334f0dc14c4b91 /riscv/sim.h | |
| parent | 65c8ac48af16235097084b413c10c7bff576b331 (diff) | |
| download | riscv-isa-sim-5c1849722546813bae3fe6002ce8961dfd14f2f1.zip riscv-isa-sim-5c1849722546813bae3fe6002ce8961dfd14f2f1.tar.gz riscv-isa-sim-5c1849722546813bae3fe6002ce8961dfd14f2f1.tar.bz2 | |
Add --dmi-rti and --abstract-rti to test OpenOCD.
Optionally make spike behave more like real hardware, to automatically
test OpenOCD's handling of such hardware.
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index e42808b..6521573 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -23,7 +23,8 @@ public: sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems, const std::vector<std::string>& args, const std::vector<int> hartids, - unsigned progsize, unsigned max_bus_master_bits, bool require_authentication); + unsigned progsize, unsigned max_bus_master_bits, + bool require_authentication, suseconds_t abstract_delay_usec); ~sim_t(); // run the simulation to completion |