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| author | Tim Newsome <tim@sifive.com> | 2016-05-01 12:05:48 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 990c6c48098e83584edf5282d119187abae04a4d (patch) | |
| tree | d2ba581b281dce0c329822f98cc7c21faf868323 /riscv/sim.h | |
| parent | 57ff1b6595e485b8b002238ddbd10483bbd62fb3 (diff) | |
| download | riscv-isa-sim-990c6c48098e83584edf5282d119187abae04a4d.zip riscv-isa-sim-990c6c48098e83584edf5282d119187abae04a4d.tar.gz riscv-isa-sim-990c6c48098e83584edf5282d119187abae04a4d.tar.bz2 | |
Have Debug memory kind of working again.
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index d3c9a6b..bd42419 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -68,9 +68,6 @@ private: reg_t mem_to_addr(char* x) { return x - mem + DRAM_BASE; } bool mmio_load(reg_t addr, size_t len, uint8_t* bytes); bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes); - // Return a pointer to the start of the page that addr falls in, or NULL if - // there is no IO device at that address. - char* mmio_page(reg_t addr); void make_config_string(); // presents a prompt for introspection into the simulation |