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author | Andy Wright <acwright@mit.edu> | 2018-05-31 13:53:12 -0400 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2018-05-31 10:53:12 -0700 |
commit | d6fcfdebf6a893bf37670fd67203d18653df4a0e (patch) | |
tree | f4b65db4f03545a10815ec021a39b8aee64f8ffc /riscv/sim.h | |
parent | 19efe7d1121ab0e1a3014a1554e7340fa958c13f (diff) | |
download | riscv-isa-sim-d6fcfdebf6a893bf37670fd67203d18653df4a0e.zip riscv-isa-sim-d6fcfdebf6a893bf37670fd67203d18653df4a0e.tar.gz riscv-isa-sim-d6fcfdebf6a893bf37670fd67203d18653df4a0e.tar.bz2 |
Put simif_t declaration in its own file. (#209)
By separating the simif_t declaration from the sim_t declaration, the
simif_t declaration no longer depends on fesvr header files. This
simplifies compilation of custom sim class implementations that don't
depend on fesvr.
Diffstat (limited to 'riscv/sim.h')
-rw-r--r-- | riscv/sim.h | 14 |
1 files changed, 1 insertions, 13 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 257de5b..97e9ede 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -6,6 +6,7 @@ #include "processor.h" #include "devices.h" #include "debug_module.h" +#include "simif.h" #include <fesvr/htif.h> #include <fesvr/context.h> #include <vector> @@ -15,19 +16,6 @@ class mmu_t; class remote_bitbang_t; -// this is the interface to the simulator used by the processors and memory -class simif_t -{ -public: - // should return NULL for MMIO addresses - virtual char* addr_to_mem(reg_t addr) = 0; - // used for MMIO addresses - virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0; - virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0; - // Callback for processors to let the simulation know they were reset. - virtual void proc_reset(unsigned id) = 0; -}; - // this class encapsulates the processors and memory in a RISC-V machine. class sim_t : public htif_t, public simif_t { |