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| author | Tim Newsome <tim@sifive.com> | 2017-02-07 11:27:48 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-02-07 11:27:48 -0800 |
| commit | 94277648d5a0bb0e8283bbb33e25f6faab11c0d6 (patch) | |
| tree | 880c0551627766238f419b4d8126e87e383f5cde /riscv/sim.h | |
| parent | 1f65ba49ea665ceed2774a1a62ac32076e4d3025 (diff) | |
| download | riscv-isa-sim-94277648d5a0bb0e8283bbb33e25f6faab11c0d6.zip riscv-isa-sim-94277648d5a0bb0e8283bbb33e25f6faab11c0d6.tar.gz riscv-isa-sim-94277648d5a0bb0e8283bbb33e25f6faab11c0d6.tar.bz2 | |
OpenOCD does a dmi read and gets dummy value back.
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index c8ba407..99b6809 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -35,6 +35,8 @@ public: const char* get_config_string() { return config_string.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } + debug_module_t debug_module; + private: char* mem; // main memory size_t memsz; // memory size in bytes @@ -44,7 +46,6 @@ private: std::unique_ptr<rom_device_t> boot_rom; std::unique_ptr<rtc_t> rtc; bus_t bus; - debug_module_t debug_module; processor_t* get_core(const std::string& i); void step(size_t n); // step through simulation |