diff options
| author | Tim Newsome <tim@sifive.com> | 2017-02-10 19:08:16 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-02-10 19:08:16 -0800 |
| commit | b4de20a92e48e9e08872323675bdd4bbf07b37d6 (patch) | |
| tree | 98507face8a876ee22ba46ecfc02814332071ba7 /riscv/sim.h | |
| parent | 8a09a059dc3ddd0b6df8028ae7e4c9e6e1c9d41e (diff) | |
| download | riscv-isa-sim-b4de20a92e48e9e08872323675bdd4bbf07b37d6.zip riscv-isa-sim-b4de20a92e48e9e08872323675bdd4bbf07b37d6.tar.gz riscv-isa-sim-b4de20a92e48e9e08872323675bdd4bbf07b37d6.tar.bz2 | |
Entering debug mode now jumps to "dynamic rom"
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 99b6809..4cb70b4 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -34,6 +34,7 @@ public: } const char* get_config_string() { return config_string.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } + unsigned nprocs() const { return procs.size(); } debug_module_t debug_module; |