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| author | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-22 13:57:56 -0700 |
|---|---|---|
| committer | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-22 14:21:54 -0700 |
| commit | 46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb (patch) | |
| tree | 1ff563929c13be279340ad439af8692d3c9913aa /riscv/sim.h | |
| parent | 693fc45eb8ccc3c9f84b898de3119a172e0776f5 (diff) | |
| download | riscv-isa-sim-46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb.zip riscv-isa-sim-46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb.tar.gz riscv-isa-sim-46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb.tar.bz2 | |
riscv: replace rtc device with a real clint implementation
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 4111caf..57bdf8c 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -40,7 +40,7 @@ private: std::vector<processor_t*> procs; std::string dts; std::unique_ptr<rom_device_t> boot_rom; - std::unique_ptr<rtc_t> rtc; + std::unique_ptr<clint_t> clint; bus_t bus; debug_module_t debug_module; |