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author | Tim Newsome <tim@sifive.com> | 2016-03-09 17:16:26 -0800 |
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committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:09 -0700 |
commit | bd17c7e5a80c21b8b7dd6be8cd24a6f89dd63bf0 (patch) | |
tree | ea18ded8e52e3c50fa7ac9c0bf901f24575fd1f5 /riscv/sim.h | |
parent | 38b8c095df4555b618bd269e3a53817c91dc893d (diff) | |
download | riscv-isa-sim-bd17c7e5a80c21b8b7dd6be8cd24a6f89dd63bf0.zip riscv-isa-sim-bd17c7e5a80c21b8b7dd6be8cd24a6f89dd63bf0.tar.gz riscv-isa-sim-bd17c7e5a80c21b8b7dd6be8cd24a6f89dd63bf0.tar.bz2 |
Add -H to start halted.
Diffstat (limited to 'riscv/sim.h')
-rw-r--r-- | riscv/sim.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 7ee4020..dad32ef 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -17,7 +17,7 @@ class mmu_t; class sim_t { public: - sim_t(const char* isa, size_t _nprocs, size_t mem_mb, + sim_t(const char* isa, size_t _nprocs, size_t mem_mb, bool halted, const std::vector<std::string>& htif_args); ~sim_t(); |