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AgeCommit message (Expand)AuthorFilesLines
2022-06-02Replaced nonstandard with non-standard.Krste Asanovic1-3/+3
2022-03-18Fix copy-paste errors in Sv57x4 descriptionAndrew Waterman1-4/+4
2022-02-24Hypervisor: use HFENCE.GVMA after PMP write to synchronize VS-enabled-G-disab...John Ingalls1-8/+5
2022-01-14hypervisor: Add Sv57 to &x4 address witdth list (#811)Dylan Reid1-1/+1
2022-01-09Clarify HLVX exception typesAndrew Waterman1-0/+4
2021-12-29Clarify handling of direct and indirect vsatp.MODE writes with Reserved values.gfavor1-4/+3
2021-12-29hypervisor: fix typos (#803)Dong Du1-2/+2
2021-12-28Clarify V=1 [v]satp write behaviorAndrew Waterman1-0/+2
2021-12-16Fix misnamed fieldAndrew Waterman1-2/+2
2021-12-15Improve HFENCE.GVMA commentaryAndrew Waterman1-6/+7
2021-12-15Provide non-normative guidance on HFENCE.GVMA TLB flushingAndrew Waterman1-0/+18
2021-12-15fix typoAndrew Waterman1-1/+1
2021-12-12Better clarify the effects of HFENCE.VVMA and HFENCE.GVMA (#794)John Hauser1-5/+4
2021-12-03Add FLH, FSH to defined transformed instructions for H extension (#792)John Hauser1-6/+6
2021-12-02Clarify that henvcfg.PBMTE is read-only zero if Svpbmt is not implementedAndrew Waterman1-0/+1
2021-11-30fix typoAndrew Waterman1-1/+1
2021-11-30Permit speculative execution of HLV/HSV; reset hgatp.MODE, satp.MODEAndrew Waterman1-21/+11
2021-11-30Change H extension to version 1.0 (#787)John Hauser1-1/+1
2021-11-29Priv specs are ratifiedAndrew Waterman1-7/+1
2021-11-29Add menvcfg.PBMTE / henvcfg.PBMTEAndrew Waterman1-3/+11
2021-11-28Add VS fieldAndrew Waterman1-3/+9
2021-11-28Split RV32 [v]sstatus figures into two rowsAndrew Waterman1-15/+28
2021-11-26Clarify when SFENCE.VMA/HFENCE.GVMA need be executedAndrew Waterman1-2/+3
2021-11-19Explain why mstatus.TVM doesn't affect vsatp, HFENCE.VVMA (#779)John Hauser1-0/+29
2021-11-18H extension requires page-based address translation (#778)John Hauser1-1/+2
2021-11-15Revert "Separate transformation for HLV instructions (#777)"Andrew Waterman1-33/+3
2021-11-15Separate transformation for HLV instructions (#777)John Hauser1-3/+33
2021-11-15Memory access traps may write zero to stval (#776)John Hauser1-1/+2
2021-11-12Rename hstatus.HU (#770)John Hauser1-1/+1
2021-11-12Allow more bits of hideleg to be writable (#772)John Hauser1-3/+4
2021-11-12Clarify condition when virtual instruction trap will occur (#773)John Hauser1-1/+1
2021-11-12CSR mideleg masks hideleg, hip, and hie (#771)John Hauser1-0/+3
2021-11-11Rewrite most instances of "hardwire" as "read-only" (#768)John Hauser1-17/+17
2021-11-02Add the Svinval standard extensionDaniel Lustig1-6/+6
2021-11-01Add Sv57 and Sv57x4Daniel Lustig1-20/+54
2021-11-01Various minor virtual memory clarificationsDaniel Lustig1-5/+43
2021-09-15Freeze the hypervisor extension, version 1.0.0-rc (#739)John Hauser1-3/+6
2021-09-14Hypervisor extension requires page-based address translation (#737)John Hauser1-1/+2
2021-09-11Rename STCE to STCD to reverse its polarityAndrew Waterman1-2/+2
2021-09-08Merge pull request #727 from riscv/mseccfgAndrew Waterman1-2/+99
2021-09-05Make virtual instruction exceptions more consistent for VU mode (#730)John Hauser1-3/+13
2021-09-01Clarify widths of privileged CSRs (#728)John Hauser1-20/+20
2021-08-29FIOM affects aq/rl, tooAndrew Waterman1-0/+5
2021-08-29Minor changes to JohnH's henvcfg specAndrew Waterman1-30/+36
2021-08-29Add CSRs henvcfg/henvcfgh to hypervisor extensionJohn Hauser1-2/+88
2021-08-18Update H chapter table of synchronous exception priorities (#717)John Hauser1-20/+19
2021-08-17Make explicit the priorities of synch. exceptions of H extension (#711)John Hauser1-0/+53
2021-08-16stval already cannot be zero on breakpoints, misaligned addresses (#714)John Hauser1-5/+2
2021-08-16VS mode should not see exception code 10 (#712)John Hauser1-0/+1
2021-08-16Insert missing commaAndrew Waterman1-1/+1
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