aboutsummaryrefslogtreecommitdiff
path: root/src/hypervisor.tex
AgeCommit message (Expand)AuthorFilesLines
2023-04-17Add the capability to build the Latex version of ISARafael Sene1-3590/+0
2023-04-17Added back the priv tex filesBill Traynor1-0/+3590
2023-04-04Removed remaining latex.Bill Traynor1-3590/+0
2023-02-28Clarify WFI trapping behavior (#972)Andrew Waterman1-0/+3
2022-07-26Replaced nonstandard with non-standard.Krste Asanovic1-3/+3
2022-07-26Fix copy-paste errors in Sv57x4 descriptionAndrew Waterman1-4/+4
2022-07-26Hypervisor: use HFENCE.GVMA after PMP write to synchronize VS-enabled-G-disab...John Ingalls1-8/+5
2022-07-26hypervisor: Add Sv57 to &x4 address witdth list (#811)Dylan Reid1-1/+1
2022-07-26Clarify HLVX exception typesAndrew Waterman1-0/+4
2022-07-26Clarify handling of direct and indirect vsatp.MODE writes with Reserved values.gfavor1-4/+3
2022-07-26hypervisor: fix typos (#803)Dong Du1-2/+2
2022-07-26Clarify V=1 [v]satp write behaviorAndrew Waterman1-0/+2
2022-07-26Fix misnamed fieldAndrew Waterman1-2/+2
2022-07-26Improve HFENCE.GVMA commentaryAndrew Waterman1-6/+7
2022-07-26Provide non-normative guidance on HFENCE.GVMA TLB flushingAndrew Waterman1-0/+18
2022-07-26fix typoAndrew Waterman1-1/+1
2022-07-26Better clarify the effects of HFENCE.VVMA and HFENCE.GVMA (#794)John Hauser1-5/+4
2022-07-26Add FLH, FSH to defined transformed instructions for H extension (#792)John Hauser1-6/+6
2022-07-26Clarify that henvcfg.PBMTE is read-only zero if Svpbmt is not implementedAndrew Waterman1-0/+1
2022-07-26fix typoAndrew Waterman1-1/+1
2022-07-26Permit speculative execution of HLV/HSV; reset hgatp.MODE, satp.MODEAndrew Waterman1-21/+11
2022-07-26Change H extension to version 1.0 (#787)John Hauser1-1/+1
2022-07-26Priv specs are ratifiedAndrew Waterman1-7/+1
2022-07-26Add menvcfg.PBMTE / henvcfg.PBMTEAndrew Waterman1-3/+11
2022-07-26Add VS fieldAndrew Waterman1-3/+9
2022-07-26Split RV32 [v]sstatus figures into two rowsAndrew Waterman1-15/+28
2022-07-26Clarify when SFENCE.VMA/HFENCE.GVMA need be executedAndrew Waterman1-2/+3
2022-07-26Explain why mstatus.TVM doesn't affect vsatp, HFENCE.VVMA (#779)John Hauser1-0/+29
2022-07-26H extension requires page-based address translation (#778)John Hauser1-1/+2
2022-07-26Revert "Separate transformation for HLV instructions (#777)"Andrew Waterman1-33/+3
2022-07-26Separate transformation for HLV instructions (#777)John Hauser1-3/+33
2022-07-26Memory access traps may write zero to stval (#776)John Hauser1-1/+2
2022-07-26Rename hstatus.HU (#770)John Hauser1-1/+1
2022-07-26Allow more bits of hideleg to be writable (#772)John Hauser1-3/+4
2022-07-26Clarify condition when virtual instruction trap will occur (#773)John Hauser1-1/+1
2022-07-26CSR mideleg masks hideleg, hip, and hie (#771)John Hauser1-0/+3
2022-07-26Rewrite most instances of "hardwire" as "read-only" (#768)John Hauser1-17/+17
2022-07-26Add the Svinval standard extensionDaniel Lustig1-6/+6
2022-07-26Add Sv57 and Sv57x4Daniel Lustig1-20/+54
2022-07-26Various minor virtual memory clarificationsDaniel Lustig1-5/+43
2021-09-15Freeze the hypervisor extension, version 1.0.0-rc (#739)John Hauser1-3/+6
2021-09-14Hypervisor extension requires page-based address translation (#737)John Hauser1-1/+2
2021-09-11Rename STCE to STCD to reverse its polarityAndrew Waterman1-2/+2
2021-09-08Merge pull request #727 from riscv/mseccfgAndrew Waterman1-2/+99
2021-09-05Make virtual instruction exceptions more consistent for VU mode (#730)John Hauser1-3/+13
2021-09-01Clarify widths of privileged CSRs (#728)John Hauser1-20/+20
2021-08-29FIOM affects aq/rl, tooAndrew Waterman1-0/+5
2021-08-29Minor changes to JohnH's henvcfg specAndrew Waterman1-30/+36
2021-08-29Add CSRs henvcfg/henvcfgh to hypervisor extensionJohn Hauser1-2/+88
2021-08-18Update H chapter table of synchronous exception priorities (#717)John Hauser1-20/+19
generated by cgit v1.1 at 2024-10-14 15:53:11 +0000