Rewrite most instances of "hardwire" as "read-only" (#768)

1 files changed, 17 insertions, 17 deletions

diff --git a/src/hypervisor.tex b/src/hypervisor.tex
index 269c809..dc93acc 100644
--- a/src/hypervisor.tex
+++ b/src/hypervisor.tex
@@ -30,8 +30,8 @@ implement the SBI for its VS-mode guest.
 The hypervisor extension depends on an ``I'' base integer ISA with
 32 {\tt x} registers (RV32I or RV64I), not RV32E, which has only
 16 {\tt x} registers.
-CSR {\tt mtval} must not be hardwired to zero, and
-{\tt satp}.MODE must not be hardwired to Bare.
+CSR {\tt mtval} must not be read-only zero, and
+{\tt satp}.MODE must not be read-only zero (only Bare).
 
 The hypervisor extension is enabled by setting bit 7 in the {\tt misa} CSR,
 which corresponds to the letter H.
@@ -293,7 +293,7 @@ and the maximum guest external interrupt number (known as GEILEN),
 inclusive.
 When VGEIN=0, no guest external interrupt source is selected for VS-level
 external interrupts.
-GEILEN may be zero, in which case VGEIN may be hardwired to zero.
+GEILEN may be zero, in which case VGEIN may be read-only zero.
 Guest external interrupts are explained in
 Section~\ref{sec:hgeinterruptregs}, and the use of VGEIN is covered
 further in Section~\ref{sec:hinterruptregs}.
@@ -431,15 +431,15 @@ Bit & Attribute   & Corresponding Exception \\
 \hline
 \end{tabular}
 \end{center}
-\caption{Bits of {\tt hedeleg} that must be writable or must be hardwired
-to zero.}
+\caption{Bits of {\tt hedeleg} that must be writable or must be read-only
+zero.}
 \label{tab:hedeleg-bits}
 \end{table*}
 
 A synchronous trap that has been delegated to HS-mode (using
 {\tt medeleg}) is further delegated to VS-mode if V=1 before the trap and
 the corresponding {\tt hedeleg} bit is set.
-Each bit of {\tt hedeleg} shall be either writable or hardwired to zero.
+Each bit of {\tt hedeleg} shall be either writable or read-only zero.
 Many bits of {\tt hedeleg} are required specifically to be writable or
 zero, as enumerated in Table~\ref{tab:hedeleg-bits}.
 Bit~0, corresponding to instruction address misaligned exceptions, must
@@ -455,7 +455,7 @@ further delegated to VS-mode if the corresponding {\tt hideleg} bit is
 set.
 Among bits 15:0 of {\tt hideleg}, only bits 10, 6, and 2 (corresponding
 to the standard VS-level interrupts) shall be writable, and the others
-shall be hardwired to zero.
+shall be read-only zero.
 
 When a virtual supervisor external interrupt (code 10) is delegated to
 VS-mode, it is automatically translated by the machine into a supervisor
@@ -473,7 +473,7 @@ interrupt causes (codes 16 and above).
 
 Register {\tt hvip} is an HSXLEN-bit read/write register that a
 hypervisor can write to indicate virtual interrupts intended for VS-mode.
-Bits of {\tt hvip} that are not writable are hardwired to zeros.
+Bits of {\tt hvip} that are not writable are read-only zeros.
 
 \begin{figure}[h!]
 {\footnotesize
@@ -569,7 +569,7 @@ HSXLEN \\
 \end{figure}
 
 For each writable bit in {\tt sie}, the corresponding bit shall be
-hardwired to zero in both {\tt hip} and {\tt hie}.
+read-only zero in both {\tt hip} and {\tt hie}.
 Hence, the nonzero bits in {\tt sie} and {\tt hie} are always mutually
 exclusive, and likewise for {\tt sip} and {\tt hip}.
 
@@ -589,7 +589,7 @@ privilege than HS-mode;
 {\tt hip} and {\tt hie}; and
 (c)~bit~\textit{i} is not set in {\tt hideleg}.
 
-If bit~\textit{i} of {\tt sie} is hardwired to zero, the same bit in
+If bit~\textit{i} of {\tt sie} is read-only zero, the same bit in
 register {\tt hip} may be writable or may be read-only.
 When bit~\textit{i} in {\tt hip} is writable, a pending interrupt
 \textit{i} can be cleared by writing 0 to this bit.
@@ -602,7 +602,7 @@ involve a call to the execution environment).
 
 A bit in {\tt hie} shall be writable if the corresponding interrupt can
 ever become pending in {\tt hip}.
-Bits of {\tt hie} that are not writable shall be hardwired to zero.
+Bits of {\tt hie} that are not writable shall be read-only zero.
 
 The standard portions (bits 15:0) of registers {\tt hip} and {\tt hie}
 are formatted as shown in Figures \ref{hipreg-standard} and
@@ -784,7 +784,7 @@ external interrupts is \unspecified\ and may be zero.
 This number is known as \textit{GEILEN}.
 The least-significant bits are implemented first, apart from bit~0.
 Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in
-{\tt hgeie}, and all other bit positions shall be hardwired to zeros in
+{\tt hgeie}, and all other bit positions shall be read-only zeros in
 both {\tt hgeip} and {\tt hgeie}.
 
 \begin{commentary}
@@ -961,7 +961,7 @@ In VU-mode, a counter is not readable unless the applicable bits are set
 in both {\tt hcounteren} and {\tt scounteren}.
 
 {\tt hcounteren} must be implemented.
-However, any of the bits may contain a hardwired value of zero,
+However, any of the bits may be read-only zero,
 indicating reads to the corresponding counter will cause an exception
 when V=1.
 Hence, they are effectively \warl\ fields.
@@ -1252,7 +1252,7 @@ virtual-memory schemes (Sv32x4, Sv39x4, Sv48x4, and Sv57x4), the root page table
 In these modes, the lowest two bits of the physical page number (PPN) in
 {\tt hgatp} always read as zeros.
 An implementation that supports only the defined paged virtual-memory schemes
-and/or Bare may hardwire PPN[1:0] to zero.
+and/or Bare may make PPN[1:0] read-only zero.
 
 The number of VMID bits is \unspecified\ and may be zero.
 The number of implemented VMID bits, termed {\mbox {\em VMIDLEN}}, may be
@@ -2218,10 +2218,10 @@ register but is not a superset of {\tt vsstatus}.
 
 When the hypervisor extension is implemented, bits 10, 6, and 2 of
 {\tt mideleg} (corresponding to the standard VS-level interrupts) are
-each hardwired to one.
+each read-only one.
 Furthermore, if any guest external interrupts are implemented (GEILEN is
 nonzero), bit~12 of {\tt mideleg} (corresponding to supervisor-level
-guest external interrupts) is also hardwired to one.
+guest external interrupts) is also read-only one.
 VS-level interrupts and guest external interrupts are always delegated
 past M-mode to HS-mode.
 
@@ -3475,7 +3475,7 @@ a simple write, is ignored for the pseudoinstruction.
 
 \begin{commentary}
 If the conditions that necessitate a pseudoinstruction value can ever
-occur for M-mode, then {\tt mtinst} cannot be hardwired entirely to zero;
+occur for M-mode, then {\tt mtinst} cannot be entirely read-only zero;
 and likewise for HS-mode and {\tt htinst}.
 However, in that case, the trap instruction registers may minimally
 support only values 0 and {\tt 0x00002000} or {\tt 0x00003000}, and