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| author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-11-12 14:59:42 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-11-12 14:59:42 -0800 |
| commit | 7664209c321a51dbbe4836afe5ddd2e984f8abb1 (patch) | |
| tree | 554ce42eed65fb458e3e9009129b28b28cd75179 /src/hypervisor.tex | |
| parent | e6bf1c56e234ceaf102e7ce5d5c93c34b393cebe (diff) | |
| download | riscv-isa-manual-7664209c321a51dbbe4836afe5ddd2e984f8abb1.zip riscv-isa-manual-7664209c321a51dbbe4836afe5ddd2e984f8abb1.tar.gz riscv-isa-manual-7664209c321a51dbbe4836afe5ddd2e984f8abb1.tar.bz2 | |
Clarify condition when virtual instruction trap will occur (#773)
Diffstat (limited to 'src/hypervisor.tex')
| -rw-r--r-- | src/hypervisor.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 9987468..cbf024a 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -2809,7 +2809,7 @@ separately. When V=1, a virtual instruction exception (code 22) is normally raised instead of an illegal instruction exception if the attempted instruction is \textit{HS-qualified} -but is prevented from executing when V=1 due to +but is prevented from executing when V=1 either due to insufficient privilege or because the instruction is expressly disabled by a supervisor or hypervisor CSR such as {\tt scounteren} or {\tt hcounteren}. An instruction is \textit{HS-qualified} if it would be valid to execute |