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author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-09-05 17:36:43 -0700 |
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committer | GitHub <noreply@github.com> | 2021-09-05 17:36:43 -0700 |
commit | 0abcad44c0b63e8f8aaf6d8f2dfac923f4312cb2 (patch) | |
tree | b0cb9548340582f6e7821029212b40b301af6b09 /src/hypervisor.tex | |
parent | 5bce9789a9183f553ca444d820e9152bde442c54 (diff) | |
download | riscv-isa-manual-0abcad44c0b63e8f8aaf6d8f2dfac923f4312cb2.zip riscv-isa-manual-0abcad44c0b63e8f8aaf6d8f2dfac923f4312cb2.tar.gz riscv-isa-manual-0abcad44c0b63e8f8aaf6d8f2dfac923f4312cb2.tar.bz2 |
Make virtual instruction exceptions more consistent for VU mode (#730)
Raise a virtual instruction exception when V = 1 if an attempted
instruction is HS-qualified but is explicitly blocked by either a
hypervisor CSR or a supervisor CSR. Previously, the document was
inconsistent whether an illegal instruction or virtual instruction
exception is raised when an instruction is blocked from executing in
VU mode solely by a supervisor CSR such as scounteren.
Diffstat (limited to 'src/hypervisor.tex')
-rw-r--r-- | src/hypervisor.tex | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 8380413..6e1c62a 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -2635,7 +2635,7 @@ raised instead of an illegal instruction exception if the attempted instruction is \textit{HS-qualified} but is prevented from executing when V=1 due to insufficient privilege or because the instruction is expressly disabled -by a hypervisor CSR such as {\tt hcounteren}. +by a supervisor or hypervisor CSR such as {\tt scounteren} or {\tt hcounteren}. An instruction is \textit{HS-qualified} if it would be valid to execute in HS-mode (for some values of the instruction's register operands), assuming fields TSR and TVM of CSR {\tt mstatus} are both zero. @@ -2670,16 +2670,26 @@ following cases: \begin{itemize} \item -in VS-mode or VU-mode, +in VS-mode, attempts to access a non-high-half counter CSR when the corresponding bit in {\tt hcounteren} is~0 and the same bit in {\tt mcounteren} is~1; \item -in VS-mode or VU-mode, if XLEN=32, attempts to access a high-half +in VS-mode, if XLEN=32, attempts to access a high-half counter CSR when the corresponding bit in {\tt hcounteren} is~0 and the same bit in {\tt mcounteren} is~1; \item +in VU-mode, attempts to access a non-high-half counter CSR when the +corresponding bit in either {\tt hcounteren} or {\tt scounteren} is~0 +and the same bit in {\tt mcounteren} is~1; + +\item +in VU-mode, if XLEN=32, attempts to access a high-half counter CSR when +the corresponding bit in either {\tt hcounteren} or {\tt scounteren} +is~0 and the same bit in {\tt mcounteren} is~1; + +\item in VS-mode or VU-mode, attempts to execute a hypervisor instruction (HLV, HLVX, HSV, or HFENCE); |