diff options
| author | Andrew Waterman <andrew@sifive.com> | 2021-08-16 20:50:49 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-16 20:50:49 -0700 |
| commit | 13b25bd06ed09f62a0510634d5528bce5e1b1c55 (patch) | |
| tree | 7a39fb8b4f868c0b15e309da88db39830bba6507 /src/hypervisor.tex | |
| parent | 955126c53f1afd8b8f7e9a6e2fb49be05f8a1b7f (diff) | |
| download | riscv-isa-manual-13b25bd06ed09f62a0510634d5528bce5e1b1c55.zip riscv-isa-manual-13b25bd06ed09f62a0510634d5528bce5e1b1c55.tar.gz riscv-isa-manual-13b25bd06ed09f62a0510634d5528bce5e1b1c55.tar.bz2 | |
Insert missing comma
Diffstat (limited to 'src/hypervisor.tex')
| -rw-r--r-- | src/hypervisor.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index d998877..f2af834 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -25,7 +25,7 @@ SBI as an OS normally does from S-mode. An HS-mode hypervisor is expected to implement the SBI for its VS-mode guest. The hypervisor extension depends on an ``I'' base integer ISA with -32 {\tt x} registers (RV32I or RV64I), not RV32E which has only +32 {\tt x} registers (RV32I or RV64I), not RV32E, which has only 16 {\tt x} registers. CSR {\tt mtval} must not be hardwired to zero. |