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author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-11-18 13:44:29 -0800 |
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committer | GitHub <noreply@github.com> | 2021-11-18 13:44:29 -0800 |
commit | ba8d12478b6c413630afb3179e1885ff1988cf20 (patch) | |
tree | 00d6331bfdb6365b527e7bcf07e565fd599e8b6f /src/hypervisor.tex | |
parent | d42b61fec322351846de72920e57966e1875bb57 (diff) | |
download | riscv-isa-manual-ba8d12478b6c413630afb3179e1885ff1988cf20.zip riscv-isa-manual-ba8d12478b6c413630afb3179e1885ff1988cf20.tar.gz riscv-isa-manual-ba8d12478b6c413630afb3179e1885ff1988cf20.tar.bz2 |
H extension requires page-based address translation (#778)
Diffstat (limited to 'src/hypervisor.tex')
-rw-r--r-- | src/hypervisor.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 42d0846..5a9be40 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -31,7 +31,8 @@ The hypervisor extension depends on an ``I'' base integer ISA with 32 {\tt x} registers (RV32I or RV64I), not RV32E, which has only 16 {\tt x} registers. CSR {\tt mtval} must not be read-only zero, and -{\tt satp}.MODE must not be read-only zero (only Bare). +standard page-based address translation must be supported, either +Sv32 for RV32, or a minimum of Sv39 for RV64. The hypervisor extension is enabled by setting bit 7 in the {\tt misa} CSR, which corresponds to the letter H. |