riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
debug	Update the debug CSR definitions for the proposed 0.13 debug spec	Palmer Dabbelt	7 years
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	2 years
master	Include rs1 values in Go instruction opcodes. (#254)	Joel Sing	8 hours
riscv-bitmanip	Remove subu.w	Andrew Waterman	4 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	2 years
rvv	Fix config imms	Colin Schmidt	5 years
v	CSRRx is called Zicsr	Andrew Waterman	6 years
vadc	Update encoding of vadc and friends	Andrew Waterman	5 years
wfmi	Add wfmi instruction	Andrew Waterman	3 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	4 years
[...]


Age	Commit message	Author	Files	Lines
2021-06-07	Add wfmi instructionwfmi	Andrew Waterman	2	-1/+2
2021-06-04	scalar-crypto: Opcode updates for v0.9.2 (#66)	Ben Marshall	4	-8/+8
2021-04-05	Add fence.tso and pause instructions	Andrew Waterman	1	-2/+2
2021-03-11	update vmv.x.s opcode (#65)	leahyao	1	-1/+1
2021-03-08	Merge pull request #63 from ben-marshall/scalar-crypto	Andrew Waterman	5	-3/+136
2021-02-24	Merge pull request #64 from chihminchao/rvv-v0.10	Andrew Waterman	2	-5/+9
2021-02-23	rvv: add vsetivli	Chih-Min Chao	2	-3/+5
2021-02-23	rvv: rename reciprocal instructions	Chih-Min Chao	1	-2/+2
2021-02-23	rvv: add vle1/vse1 instructions	Chih-Min Chao	1	-0/+2
2021-02-19	scalar-crypto: Apply suggestions from code review	Ben Marshall	3	-5/+2
[...]