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AgeCommit message (Expand)AuthorFilesLines
2019-11-04Update encoding of vadc and friendsvadcAndrew Waterman1-10/+10
2019-09-17vwmaccsu/us opcodes have been swappedAndrew Waterman1-6/+6
2019-09-12fesvr no longer needs encoding.hAndrew Waterman1-3/+2
2019-09-12Add PAUSE hint instructionAndrew Waterman1-0/+1
2019-08-26More updates to rvv encodingAndrew Waterman1-13/+11
2019-08-03Fix crash introduced by #30Andrew Waterman1-1/+1
2019-08-03(Partially) fix #30 (#31)Tommy Thorn3-42/+47
2019-07-15vext.x.v -> vmv.x.sAndrew Waterman1-1/+1
2019-07-05Fix encoding of vfclass.v instructionAndrew Waterman1-1/+1
2019-06-28vmpopc/vmfirst -> vpopc/vfirst; move to VMUNARY0 opcodeAndrew Waterman1-2/+2
2019-06-19Remove redundant entry from MakefileAndrew Waterman1-1/+1
2019-06-18v-spec 0.7.1-0607 (#29)Chih-Min Chao2-41/+74
2019-06-18Add pseudos for RV32 shifts with correct immediate constraintAndrew Waterman2-1/+6
2019-06-16More hypervisor v0.4 updatesAndrew Waterman2-3/+3
2019-06-16Updates for hypervisor v0.4Andrew Waterman1-13/+14
2019-06-11Expand vfunary0 and vfunary1 opcodes into sub-instructionsAndrew Waterman1-2/+20
2019-06-05More V 0.7.1 updatesAndrew Waterman1-12/+10
2019-06-05Some V 0.7.1 updatesAndrew Waterman2-19/+18
2019-06-05VMV.S.X requires vs2=0Andrew Waterman1-2/+2
2019-05-17Merge branch 'chihminchao-rvv-spec-0.7'Andrew Waterman4-4/+414
2019-05-17Expand vmunary0 into its constituent instructionsAndrew Waterman1-1/+6
2019-05-17vmv/vext/vfmv are reserved when vm=0Andrew Waterman1-4/+4
2019-05-17vadc/vsbc require vm=1Andrew Waterman1-5/+5
2019-05-17Add pseudos for masked/unmasked vmerge to help with decodingAndrew Waterman2-2/+12
2019-05-16rvv: vector instruction encodingChih-Min Chao2-2/+380
2019-05-16rvv: add vector register field and control registerChih-Min Chao1-1/+18
2019-05-14zimm -> uimm in CSR instruction listingAndrew Waterman1-2/+2
2019-04-26Create RVQ listing in latex tableAndrew Waterman1-0/+16
2019-04-24Add RV128 opcodes (#26)Rustem Yunusov2-4/+10
2019-04-23Updated path to FESVR_H in Makefile (#25)Torbjørn1-1/+1
2019-04-22Add missing N-extension CSRsAndrew Waterman1-0/+8
2019-02-28Read opcodes from files (#23)Pavel I. Kryukov1-61/+74
2019-02-11Add SystemVerilog generation (#24)Florian Zaruba2-0/+24
2019-01-22Add tentative CSR assignment for fast-interrupt group's CLIC proposalAndrew Waterman1-0/+17
2019-01-21Add tentative hypervisor CSR and instruction encodingsAndrew Waterman2-1/+23
2018-11-20Don't label latex tablesAndrew Waterman1-1/+0
2018-11-20Exclude ECALL/EBREAK from privileged instruction tableAndrew Waterman1-3/+1
2018-11-19Modernize to Python 3 (#22)Pavel I. Kryukov1-111/+114
2018-11-06Separate FENCE.I and CSRRx from RV32I tableAndrew Waterman1-9/+15
2018-09-20Add header following Go convention for generated code (#21)Tobias Klauser1-1/+1
2018-09-10Include RVC pseudos in chisel decoderAndrew Waterman1-1/+1
2018-08-25Improve TeX output for FENCE instructionsAndrew Waterman2-3/+3
2018-08-06FENCE has a field called FM in bits 31:28Andrew Waterman2-2/+3
2018-07-17Make the hashbang portable (#20)Edward Tomasz Napierała1-1/+1
2018-04-25Add proposed FENCE.TSO encodingAndrew Waterman1-0/+3
2017-12-27Use old C style comments. (#18)Tim Newsome1-11/+11
2017-11-27Rename sptbr to satp and sbadaddr to stvalAndrew Waterman2-18/+18
2017-11-27Don't copy encoding.h to binutils anymoreAndrew Waterman1-4/+0
2017-11-27Generate encoding.h for OpenOCD as well. (#16)Tim Newsome1-2/+3
2017-05-17Merge remote-tracking branch 'origin/priv-1.10'Palmer Dabbelt5-48/+87
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