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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-25 12:28:23 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-25 12:28:35 -0700 |
| commit | af61a81535e6ee3fa486057f0d2dbca04a8bd5b7 (patch) | |
| tree | 228ebedbe40fd98e58d430cfa87323d37b36160c | |
| parent | 0ce3ec1f7d82d5449ba5d00302270076f6cc34f6 (diff) | |
| download | riscv-opcodes-zfh.zip riscv-opcodes-zfh.tar.gz riscv-opcodes-zfh.tar.bz2 | |
Add tentative RV32Zfh encodingzfh
This is just a placeholder; it may well change before standardization.
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | opcodes-rv32d-zfh | 2 | ||||
| -rw-r--r-- | opcodes-rv32q-zfh | 2 | ||||
| -rw-r--r-- | opcodes-rv32zfh | 34 | ||||
| -rw-r--r-- | opcodes-rv64zfh | 7 |
5 files changed, 46 insertions, 1 deletions
@@ -5,7 +5,7 @@ PK_H := ../riscv-pk/machine/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h -ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv128q opcodes-system +ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv128q opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-system ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-rv128c opcodes-custom opcodes-rvv ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo diff --git a/opcodes-rv32d-zfh b/opcodes-rv32d-zfh new file mode 100644 index 0000000..02071ad --- /dev/null +++ b/opcodes-rv32d-zfh @@ -0,0 +1,2 @@ +fcvt.h.d rd rs1 24..20=1 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.d.h rd rs1 24..20=2 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 diff --git a/opcodes-rv32q-zfh b/opcodes-rv32q-zfh new file mode 100644 index 0000000..265bfb4 --- /dev/null +++ b/opcodes-rv32q-zfh @@ -0,0 +1,2 @@ +fcvt.h.q rd rs1 24..20=3 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.q.h rd rs1 24..20=2 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 diff --git a/opcodes-rv32zfh b/opcodes-rv32zfh new file mode 100644 index 0000000..3a47671 --- /dev/null +++ b/opcodes-rv32zfh @@ -0,0 +1,34 @@ +fadd.h rd rs1 rs2 31..27=0x00 rm 26..25=2 6..2=0x14 1..0=3 +fsub.h rd rs1 rs2 31..27=0x01 rm 26..25=2 6..2=0x14 1..0=3 +fmul.h rd rs1 rs2 31..27=0x02 rm 26..25=2 6..2=0x14 1..0=3 +fdiv.h rd rs1 rs2 31..27=0x03 rm 26..25=2 6..2=0x14 1..0=3 +fsgnj.h rd rs1 rs2 31..27=0x04 14..12=0 26..25=2 6..2=0x14 1..0=3 +fsgnjn.h rd rs1 rs2 31..27=0x04 14..12=1 26..25=2 6..2=0x14 1..0=3 +fsgnjx.h rd rs1 rs2 31..27=0x04 14..12=2 26..25=2 6..2=0x14 1..0=3 +fmin.h rd rs1 rs2 31..27=0x05 14..12=0 26..25=2 6..2=0x14 1..0=3 +fmax.h rd rs1 rs2 31..27=0x05 14..12=1 26..25=2 6..2=0x14 1..0=3 +fcvt.h.s rd rs1 24..20=0 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.s.h rd rs1 24..20=2 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +fsqrt.h rd rs1 24..20=0 31..27=0x0B rm 26..25=2 6..2=0x14 1..0=3 + +fle.h rd rs1 rs2 31..27=0x14 14..12=0 26..25=2 6..2=0x14 1..0=3 +flt.h rd rs1 rs2 31..27=0x14 14..12=1 26..25=2 6..2=0x14 1..0=3 +feq.h rd rs1 rs2 31..27=0x14 14..12=2 26..25=2 6..2=0x14 1..0=3 + +fcvt.w.h rd rs1 24..20=0 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.wu.h rd rs1 24..20=1 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fmv.x.h rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=2 6..2=0x14 1..0=3 +fclass.h rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=2 6..2=0x14 1..0=3 + +fcvt.h.w rd rs1 24..20=0 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fmv.h.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3 + +flh rd rs1 imm12 14..12=1 6..2=0x01 1..0=3 + +fsh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x09 1..0=3 + +fmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x10 1..0=3 +fmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x11 1..0=3 +fnmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x12 1..0=3 +fnmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x13 1..0=3 diff --git a/opcodes-rv64zfh b/opcodes-rv64zfh new file mode 100644 index 0000000..5cc9f25 --- /dev/null +++ b/opcodes-rv64zfh @@ -0,0 +1,7 @@ +# RV64Zfh additions to RV32Zfh + +fcvt.l.h rd rs1 24..20=2 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.lu.h rd rs1 24..20=3 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 + +fcvt.h.l rd rs1 24..20=2 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 |