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| author | Andrew Waterman <andrew@sifive.com> | 2018-11-06 19:16:54 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-06 19:16:54 -0800 |
| commit | 8f474fca1482b49a1cc0e5b45e788e8564ff6568 (patch) | |
| tree | f5e3afc3ade906c2ae188f2de902dc8b3cd0c31f | |
| parent | 835b8658e12ac2374598a086b542a4d564c6ed45 (diff) | |
| download | riscv-opcodes-v.zip riscv-opcodes-v.tar.gz riscv-opcodes-v.tar.bz2 | |
CSRRx is called Zicsrv
| -rwxr-xr-x | parse-opcodes | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/parse-opcodes b/parse-opcodes index eeae739..9f5d74a 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -869,7 +869,7 @@ def make_latex_table(): print_insts('addw', 'subw', 'sllw', 'srlw', 'sraw') print_subtitle('RV32/RV64 \emph{Zifencei} Standard Extension') print_insts('fence.i') - print_subtitle('RV32/RV64 Control and Status Register Access Instructions') + print_subtitle('RV32/RV64 \emph{Zicsr} Standard Extension') print_insts('csrrw', 'csrrs', 'csrrc') print_insts('csrrwi', 'csrrsi', 'csrrci') print_subtitle('RV32M Standard Extension') |