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| author | Andrew Waterman <andrew@sifive.com> | 2021-11-08 18:43:43 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-02-21 22:27:04 -0800 |
| commit | 71cd23ab5d25cd8f5db26cb254245d8424bf854d (patch) | |
| tree | 73e3274520f7f1dd872912296cfc917b802b0315 | |
| parent | 2497a8cc120a9d30d0cc9bf01372dc2efbefbc25 (diff) | |
| download | riscv-opcodes-rnmi.zip riscv-opcodes-rnmi.tar.gz riscv-opcodes-rnmi.tar.bz2 | |
Add RNMI CSRs and instructionrnmi
Don't merge yet; it's still early days for this extension.
| -rw-r--r-- | opcodes-system | 1 | ||||
| -rwxr-xr-x | parse_opcodes | 6 |
2 files changed, 6 insertions, 1 deletions
diff --git a/opcodes-system b/opcodes-system index aa26e38..33e4745 100644 --- a/opcodes-system +++ b/opcodes-system @@ -3,6 +3,7 @@ ecall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 ebreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 +mnret 11..7=0 19..15=0 31..20=0x702 14..12=0 6..2=0x1C 1..0=3 dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3 wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3 diff --git a/parse_opcodes b/parse_opcodes index 5f2ebb8..752c565 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -206,6 +206,10 @@ csrs = [ (0x344, 'mip'), (0x34a, 'mtinst'), (0x34b, 'mtval2'), + (0x350, 'mnscratch'), + (0x351, 'mnepc'), + (0x352, 'mncause'), + (0x353, 'mnstatus'), (0x3a0, 'pmpcfg0'), (0x3a1, 'pmpcfg1'), (0x3a2, 'pmpcfg2'), @@ -895,7 +899,7 @@ def print_insts(*names): def make_supervisor_latex_table(): print_header('r', 'i') print_subtitle('Trap-Return Instructions') - print_insts('sret', 'mret') + print_insts('sret', 'mret', 'mnret') print_subtitle('Interrupt-Management Instructions') print_insts('wfi') print_subtitle('Supervisor Memory-Management Instructions') |