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| author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-03-07 16:36:54 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-03-07 16:36:54 -0800 |
| commit | 388bb93d4e23ad0a837dd2f9df1f3c9d1115ebfa (patch) | |
| tree | b532eaa92a3e623a7b374fc7ee0fd67d53118bd9 | |
| parent | 3c1a9110b71658f6e3249186e8b44e7474a4ee90 (diff) | |
| download | riscv-opcodes-debug.zip riscv-opcodes-debug.tar.gz riscv-opcodes-debug.tar.bz2 | |
Update the debug CSR definitions for the proposed 0.13 debug specdebug
| -rw-r--r-- | encoding.h | 3 |
1 files changed, 0 insertions, 3 deletions
@@ -35,8 +35,6 @@ #define SSTATUS64_SD 0x8000000000000000 #define DCSR_XDEBUGVER (3U<<30) -#define DCSR_NDRESET (1<<29) -#define DCSR_FULLRESET (1<<28) #define DCSR_EBREAKM (1<<15) #define DCSR_EBREAKH (1<<14) #define DCSR_EBREAKS (1<<13) @@ -44,7 +42,6 @@ #define DCSR_STOPCYCLE (1<<10) #define DCSR_STOPTIME (1<<9) #define DCSR_CAUSE (7<<6) -#define DCSR_DEBUGINT (1<<5) #define DCSR_HALT (1<<3) #define DCSR_STEP (1<<2) #define DCSR_PRV (3<<0) |