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| author | Andrew Waterman <andrew@sifive.com> | 2020-11-13 17:15:44 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-11-13 17:15:44 -0800 |
| commit | 76bc8253577b570e75febb6b7c3a879b1d23e11f (patch) | |
| tree | 3186b545a180164e127933821fb50f3ec3c80ee8 | |
| parent | 0ad043ce9f0b5c1dbd29b05f54614b693f1133be (diff) | |
| download | riscv-opcodes-riscv-bitmanip.zip riscv-opcodes-riscv-bitmanip.tar.gz riscv-opcodes-riscv-bitmanip.tar.bz2 | |
Remove subu.wriscv-bitmanip
See https://github.com/riscv/riscv-bitmanip/pull/89
| -rw-r--r-- | opcodes-rv64b | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/opcodes-rv64b b/opcodes-rv64b index 160dd24..59d0172 100644 --- a/opcodes-rv64b +++ b/opcodes-rv64b @@ -13,7 +13,6 @@ slliu.w rd rs1 31..26=2 shamt 14..12=1 6..2=0x06 1..0=3 addwu rd rs1 rs2 31..25=5 14..12=0 6..2=0x0E 1..0=3 subwu rd rs1 rs2 31..25=37 14..12=0 6..2=0x0E 1..0=3 addu.w rd rs1 rs2 31..25=4 14..12=0 6..2=0x0E 1..0=3 -subu.w rd rs1 rs2 31..25=36 14..12=0 6..2=0x0E 1..0=3 slow rd rs1 rs2 31..25=16 14..12=1 6..2=0x0E 1..0=3 srow rd rs1 rs2 31..25=16 14..12=5 6..2=0x0E 1..0=3 |