riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
debug	Update the debug CSR definitions for the proposed 0.13 debug spec	Palmer Dabbelt	7 years
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	2 years
master	Include rs1 values in Go instruction opcodes. (#254)	Joel Sing	7 hours
riscv-bitmanip	Remove subu.w	Andrew Waterman	4 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	2 years
rvv	Fix config imms	Colin Schmidt	5 years
v	CSRRx is called Zicsr	Andrew Waterman	6 years
vadc	Update encoding of vadc and friends	Andrew Waterman	5 years
wfmi	Add wfmi instruction	Andrew Waterman	3 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	4 years
[...]


Age	Commit message	Author	Files	Lines
2019-11-04	Update encoding of vadc and friendsvadc	Andrew Waterman	1	-10/+10
2019-09-17	vwmaccsu/us opcodes have been swapped	Andrew Waterman	1	-6/+6
2019-09-12	fesvr no longer needs encoding.h	Andrew Waterman	1	-3/+2
2019-09-12	Add PAUSE hint instruction	Andrew Waterman	1	-0/+1
2019-08-26	More updates to rvv encoding	Andrew Waterman	1	-13/+11
2019-08-03	Fix crash introduced by #30	Andrew Waterman	1	-1/+1
2019-08-03	(Partially) fix #30 (#31)	Tommy Thorn	3	-42/+47
2019-07-15	vext.x.v -> vmv.x.s	Andrew Waterman	1	-1/+1
2019-07-05	Fix encoding of vfclass.v instruction	Andrew Waterman	1	-1/+1
2019-06-28	vmpopc/vmfirst -> vpopc/vfirst; move to VMUNARY0 opcode	Andrew Waterman	1	-2/+2
[...]