riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
debug	Update the debug CSR definitions for the proposed 0.13 debug spec	Palmer Dabbelt	7 years
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	2 years
master	Merge pull request #257 from ved-rivos/smdbltrp1	Andrew Waterman	2 days
riscv-bitmanip	Remove subu.w	Andrew Waterman	4 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	2 years
rvv	Fix config imms	Colin Schmidt	5 years
v	CSRRx is called Zicsr	Andrew Waterman	6 years
vadc	Update encoding of vadc and friends	Andrew Waterman	5 years
wfmi	Add wfmi instruction	Andrew Waterman	3 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	4 years
[...]


Age	Commit message	Author	Files	Lines
2018-11-06	CSRRx is called Zicsrv	Andrew Waterman	1	-1/+1
2018-11-06	Split V table from rest of table	Andrew Waterman	1	-1/+4
2018-11-06	Updates from most recent meeting	Andrew Waterman	2	-7/+12
2018-11-06	V extension WIP	Andrew Waterman	4	-10/+217
2018-11-06	Separate FENCE.I and CSRRx from RV32I table	Andrew Waterman	1	-9/+15
2018-09-20	Add header following Go convention for generated code (#21)	Tobias Klauser	1	-1/+1
2018-09-10	Include RVC pseudos in chisel decoder	Andrew Waterman	1	-1/+1
2018-08-25	Improve TeX output for FENCE instructions	Andrew Waterman	2	-3/+3
2018-08-06	FENCE has a field called FM in bits 31:28	Andrew Waterman	2	-2/+3
2018-07-17	Make the hashbang portable (#20)	Edward Tomasz Napierała	1	-1/+1
[...]