riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
debug	Update the debug CSR definitions for the proposed 0.13 debug spec	Palmer Dabbelt	7 years
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	2 years
master	Include rs1 values in Go instruction opcodes. (#254)	Joel Sing	8 hours
riscv-bitmanip	Remove subu.w	Andrew Waterman	4 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	2 years
rvv	Fix config imms	Colin Schmidt	5 years
v	CSRRx is called Zicsr	Andrew Waterman	6 years
vadc	Update encoding of vadc and friends	Andrew Waterman	5 years
wfmi	Add wfmi instruction	Andrew Waterman	3 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	4 years
[...]


Age	Commit message	Author	Files	Lines
2022-02-21	Add RNMI CSRs and instructionrnmi	Andrew Waterman	2	-1/+6
2022-02-13	Clean up handling of bitmanip extensions	Andrew Waterman	13	-92/+120
2022-01-20	Synchronize priv-instr-table.tex with the Manual (#99)	Tsukasa #01 (a4lg)	1	-7/+14
2022-01-19	Update vmorn/vmandn mnemonics; create pseudos for old names	Andrew Waterman	2	-2/+5
2022-01-19	Fix encodings of HINVAL.VVMA/HINVAL.GVMA	Andrew Waterman	1	-2/+2
2022-01-19	Add RISC-V Zfh extension instructions to table (#97)	Tsukasa #01 (a4lg)	1	-0/+17
2022-01-19	Remove LaTeX trailing spaces (entirely) (#98)	Tsukasa #01 (a4lg)	1	-16/+16
2021-12-21	removed non-ratified RV64B opcodes (#96)	Purushothaman Palani	1	-7/+0
2021-12-16	Add new CSR bits defined in Privileged Spec version 1.12 (#94)	Tsukasa #01 (a4lg)	1	-0/+31
2021-12-15	Merge branch 'a4lg-make-intermediate-header'	Andrew Waterman	2	-3/+6
[...]