riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
debug	Update the debug CSR definitions for the proposed 0.13 debug spec	Palmer Dabbelt	7 years
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	2 years
master	Merge pull request #257 from ved-rivos/smdbltrp1	Andrew Waterman	2 days
riscv-bitmanip	Remove subu.w	Andrew Waterman	4 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	2 years
rvv	Fix config imms	Colin Schmidt	5 years
v	CSRRx is called Zicsr	Andrew Waterman	6 years
vadc	Update encoding of vadc and friends	Andrew Waterman	5 years
wfmi	Add wfmi instruction	Andrew Waterman	3 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	4 years
[...]


Age	Commit message	Author	Files	Lines
2020-11-13	Remove subu.wriscv-bitmanip	Andrew Waterman	1	-1/+0
2020-11-13	Update minu/max encodings	Andrew Waterman	1	-2/+2
2020-06-10	Rebase d242e1ed7 onto master	Andrew Waterman	3	-1/+133
2020-05-12	RVV v0.9: AMOs with explicit element widths	Andrew Waterman	1	-19/+39
2020-05-12	RVV v0.9: loads/stores with explicit element widths	Andrew Waterman	1	-45/+33
2020-05-12	RVV v0.9: change vl1r/vs1r opcodes	Andrew Waterman	1	-2/+2
2020-05-12	RVV v0.9: new extension instructions	Andrew Waterman	1	-0/+9
2020-05-12	RVV v0.9: move VFUNARY0/VFUNARY1 opcodes	Andrew Waterman	1	-26/+26
2020-05-04	Add DCSR_CAUSE_GROUP. (#44)	Tim Newsome	1	-0/+1
2020-04-14	rvv: add new vcsr for vector spec 0.9 (#42)	Chih-Min Chao	1	-0/+1
[...]