riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
debug	Update the debug CSR definitions for the proposed 0.13 debug spec	Palmer Dabbelt	8 years
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	3 years
master	Merge pull request #316 from Myrausman/repo_structure	Andrew Waterman	25 hours
riscv-bitmanip	Remove subu.w	Andrew Waterman	4 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	3 years
rvv	Fix config imms	Colin Schmidt	6 years
v	CSRRx is called Zicsr	Andrew Waterman	6 years
vadc	Update encoding of vadc and friends	Andrew Waterman	5 years
wfmi	Add wfmi instruction	Andrew Waterman	3 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	5 years
[...]


Age	Commit message	Author	Files	Lines
2022-05-02	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...incoresemi-migration-to-new-format	Andrew Waterman	113	-1867/+2484
2022-05-02	adding support for spinalhdl code generation	Neel Gala	4	-6/+20
2022-05-02	adding python dependencies to requirements.txt	Neel Gala	2	-4/+13
2022-05-02	adding backward compatible makefile targets	Neel Gala	1	-8/+16
2022-04-30	add spinalhdl support (#108)	Ncerzzk	3	-3/+28
2022-04-11	remove custom opcodes	Neel Gala	1	-27/+0
2022-04-11	update github actions yaml with new command line	Neel Gala	1	-2/+2
2022-04-11	migrate V-extension aliases	Neel Gala	2	-18/+18
2022-04-08	pass only fence_tso and pause to rv32i latex table	Neel Gala	1	-1/+2
2022-04-08	change xperm.[nbhw] to xperm[4,8,16,32]	Neel Gala	6	-12/+12
[...]