riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
debug	Update the debug CSR definitions for the proposed 0.13 debug spec	Palmer Dabbelt	7 years
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	2 years
master	Include rs1 values in Go instruction opcodes. (#254)	Joel Sing	7 hours
riscv-bitmanip	Remove subu.w	Andrew Waterman	4 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	2 years
rvv	Fix config imms	Colin Schmidt	5 years
v	CSRRx is called Zicsr	Andrew Waterman	6 years
vadc	Update encoding of vadc and friends	Andrew Waterman	5 years
wfmi	Add wfmi instruction	Andrew Waterman	3 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	4 years
[...]


Age	Commit message	Author	Files	Lines
2017-03-07	Update the debug CSR definitions for the proposed 0.13 debug specdebug	Palmer Dabbelt	1	-3/+0
2016-12-21	Add Q extension	Kito Cheng	1	-0/+39
2016-12-21	Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 space	Kito Cheng	1	-1/+1
2016-12-06	avoid non-standard predefined macros	Andrew Waterman	1	-1/+1
2016-08-26	Renumber misa; add performance counter CSRs	Andrew Waterman	1	-33/+154
2016-08-26	Add mcontrol type constants. (#11)	Tim Newsome	1	-0/+3
2016-08-25	Re-rename trigger registers to be 1-based	Andrew Waterman	1	-3/+3
2016-08-25	Make hardware triggers match latest spec.	Tim Newsome	2	-22/+34
2016-07-06	Update to new PTE format	Andrew Waterman	1	-33/+10
2016-06-30	Remove instructions from privilege spec that are already in user spec	Andrew Waterman	1	-5/+2
[...]