riscv-tools/riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
debug	Update the debug CSR definitions for the proposed 0.13 debug spec	Palmer Dabbelt	7 years
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	2 years
master	Merge pull request #258 from moscickimilosz/parse_windows_fix	Andrew Waterman	7 hours
riscv-bitmanip	Remove subu.w	Andrew Waterman	4 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	2 years
rvv	Fix config imms	Colin Schmidt	5 years
v	CSRRx is called Zicsr	Andrew Waterman	6 years
vadc	Update encoding of vadc and friends	Andrew Waterman	5 years
wfmi	Add wfmi instruction	Andrew Waterman	3 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	4 years
[...]


Age	Commit message	Author	Files	Lines
2013-11-29	Add vsetprec instructionconfprec	Quan Nguyen	1	-0/+1
2013-11-24	Merge branch 'master' into confprec	Quan Nguyen	5	-59/+100
2013-11-24	Add line in Makefile to parse confprec	Quan Nguyen	1	-0/+1
2013-11-22	add missing imm for stores	Yunsup Lee	2	-6/+7
2013-11-21	fix slli/slliw encoding bug	Yunsup Lee	4	-7/+8
2013-10-29	changes to the instr-table	Yunsup Lee	2	-45/+85
2013-10-27	Move half-precision opcodes to opcodes-hwacha-ut	Quan Nguyen	3	-41/+57
2013-10-27	Merge branch 'master' of github.com:ucb-bar/riscv-opcodes into confprec	Quan Nguyen	1	-0/+1
2013-10-18	add gitignore	Yunsup Lee	1	-0/+1
2013-10-17	Add half-precision floating-point instructions	Quan Nguyen	2	-2/+44
[...]