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path: root/gcc/config/aarch64/predicates.md
AgeCommit message (Expand)AuthorFilesLines
2018-05-24PR target/83009: Relax strict address checking for store pair lanesAndre Vieira1-1/+1
2018-05-22[AArch64] Merge stores of D-register values with different modesJackson Woodruff1-0/+4
2018-03-07re PR target/84565 (ICE in extract_insn, at recog.c:2304 on aarch64)Jakub Jelinek1-1/+1
2018-02-01[AArch64] Handle SVE subregs that are effectively REVsRichard Sandiford1-0/+4
2018-01-17[AArch64] PR82964: Fix 128-bit immediate ICEsWilco Dijkstra1-7/+6
2018-01-13Add support for SVE gather loadsRichard Sandiford1-0/+8
2018-01-13[AArch64] SVE load/store_lanes supportRichard Sandiford1-0/+8
2018-01-13[AArch64] Add SVE supportRichard Sandiford1-22/+176
2018-01-11aarch64-modes.def (V2HF): New VECTOR_MODE.Michael Collison1-0/+12
2018-01-03[AArch64] Rewrite aarch64_simd_valid_immediateRichard Sandiford1-4/+4
2018-01-03Update copyright years.Jakub Jelinek1-1/+1
2017-12-21[AArch64] Tweak aarch64_classify_address interfaceRichard Sandiford1-4/+4
2017-11-08[AArch64] Add STP pattern to store a vec_concat of two 64-bit registersKyrylo Tkachov1-0/+7
2017-11-08Simplify vec_merge of vec_duplicate with const_vectorKyrylo Tkachov1-0/+3
2017-10-06Committed on behalf of Sudi DasSudakshina Das1-4/+6
2017-10-04[PATCH][AArch64] Add BIC-imm and ORR-imm SIMD patternSudakshina Das1-0/+10
2017-08-11aarch64.md (mov<mode>): Change.Tamar Christina1-5/+0
2017-07-28aarch64.md (mov<mode>): Generalize.Tamar Christina1-0/+5
2017-07-27[PATCH][AArch64] Fix missing optimization for CMP+ANDKyrylo Tkachov1-0/+4
2017-06-29re PR target/70119 (AArch64 should take advantage of implicit truncation of v...Kyrylo Tkachov1-0/+4
2017-06-05[AArch64] Use SUBS for parallel subtraction and comparison with immediateKyrylo Tkachov1-0/+4
2017-05-04[AArch64] Accept more addressing modes for PRFMKyrylo Tkachov1-0/+3
2017-01-01Update copyright years.Jakub Jelinek1-1/+1
2016-11-232016-11-22 Michael Collison <michael.collison@arm.com>Michael Collison1-0/+4
2016-11-17[AArch64] Fix gcc.dg/torture/float32-builtin.c with RTL checkingKyrylo Tkachov1-3/+3
2016-08-12re PR c/7652 (-Wswitch-break : Warn if a switch case falls through)Marek Polacek1-0/+2
2016-04-01[AArch64] Fix SIMD predicateEvandro Menezes1-1/+1
2016-02-17[AArch64] PR target/69161: Don't use special predicate for CCmode comparisons...Kyrylo Tkachov1-2/+11
2016-01-28re PR target/69305 (wrong code with -O and int128 @ aarch64)Richard Henderson1-0/+19
2016-01-19[Patch 1/4] Simplify the representation of CCMP patterns by usingWilco Dijkstra1-17/+0
2016-01-18re PR target/69176 (ICE in in final_scan_insn, at final.c:2981 on aarch64-lin...Richard Henderson1-0/+4
2016-01-04Update copyright years.Jakub Jelinek1-1/+1
2015-11-24[AArch64][v2] Improve comparison with complex immediates followed by branch/csetKyrylo Tkachov1-0/+5
2015-11-09[AArch64] PR target/68129: Define TARGET_SUPPORTS_WIDE_INTKyrylo Tkachov1-1/+1
2015-10-20[AArch64][1/2] Add fmul-by-power-of-2+fcvt optimisationKyrylo Tkachov1-0/+7
2015-09-24[AArch64] Delete aarch64_symbol_context which is not usedJiong Wang1-2/+2
2015-09-14[AArch64] Handle literal pools for functions > 1 MiB in size.Ramana Radhakrishnan1-0/+4
2015-01-05Update copyright years.Jakub Jelinek1-1/+1
2014-11-17aarch64-protos.h (aarch64_ccmp_mode_to_code): New.Zhenqiang Chen1-0/+5
2014-11-17aarch64-modes.def: Define ccmp CC mode.Zhenqiang Chen1-0/+17
2014-11-17constraints.md (Usn, [...]): New constraints.Zhenqiang Chen1-0/+8
2014-09-25[AArch64] Tighten predicates on SIMD shift intrinsicsJames Greenhalgh1-0/+53
2014-09-05[PATCH AArch64 1/2] Improve codegen of vector compares inc. tst instructionAlan Lawrence1-0/+6
2014-09-02[AArch64] Use CC_Z and CC_NZ with csinc and similar instructions.Kyrylo Tkachov1-0/+12
2014-08-01[AArch64][2/2] Add constrain to address offset in storewb_pair/loadwb_pair insnsJiong Wang1-0/+4
2014-07-31[AArch64_be] Fix vec_select hi/lo mask confusions.James Greenhalgh1-49/+2
2014-05-23[AARCH64] Support tail indirect function call.Jiong Wang1-0/+4
2014-01-23[PATCH][AArch64] Vector shift by 64 fixAlex Velenko1-0/+4
2014-01-02Update copyright years in gcc/Richard Sandiford1-1/+1
2013-08-27aarch64.md (unspec): Add UNSPEC_SISD_SSHL...Vidya Praveen1-0/+5
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