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| author | Vidya Praveen <vidyapraveen@arm.com> | 2013-08-27 11:50:26 +0100 |
|---|---|---|
| committer | Vidya Praveen <vp@gcc.gnu.org> | 2013-08-27 11:50:26 +0100 |
| commit | 2e100703fa86b17b9c05011fc73d0a8adf555908 (patch) | |
| tree | df24a9554d92f8cbb0f4fd25a81861117939c839 /gcc/config/aarch64/predicates.md | |
| parent | 4ded82768aaa1e00d3cda62ee66f2e5cd767ceb9 (diff) | |
| download | gcc-2e100703fa86b17b9c05011fc73d0a8adf555908.zip gcc-2e100703fa86b17b9c05011fc73d0a8adf555908.tar.gz gcc-2e100703fa86b17b9c05011fc73d0a8adf555908.tar.bz2 | |
aarch64.md (unspec): Add UNSPEC_SISD_SSHL...
gcc/
2013-08-27 Vidya Praveen <vidyapraveen@arm.com>
* config/aarch64/aarch64.md (unspec): Add UNSPEC_SISD_SSHL,
UNSPEC_SISD_USHL, UNSPEC_USHL_2S, UNSPEC_SSHL_2S, UNSPEC_SISD_NEG.
(<optab><mode>3_insn): Remove.
(aarch64_ashl_sisd_or_int_<mode>3): New Pattern.
(aarch64_lshr_sisd_or_int_<mode>3): Likewise.
(aarch64_ashr_sisd_or_int_<mode>3): Likewise.
(define_split for aarch64_lshr_sisd_or_int_di3): Likewise.
(define_split for aarch64_lshr_sisd_or_int_si3): Likewise.
(define_split for aarch64_ashr_sisd_or_int_di3): Likewise.
(define_split for aarch64_ashr_sisd_or_int_si3): Likewise.
(aarch64_sisd_ushl, aarch64_sisd_sshl): Likewise.
(aarch64_ushl_2s, aarch64_sshl_2s, aarch64_sisd_neg_qi): Likewise.
(ror<mode>3_insn): Likewise.
* config/aarch64/predicates.md (aarch64_simd_register): New.
gcc/testsuite/
2013-08-27 Vidya Praveen <vidyapraveen@arm.com>
* gcc.target/aarch64/scalar_shift_1.c: New.
From-SVN: r202020
Diffstat (limited to 'gcc/config/aarch64/predicates.md')
| -rw-r--r-- | gcc/config/aarch64/predicates.md | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 3e2b6b3..dbc9082 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -26,6 +26,11 @@ && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))) ) +(define_predicate "aarch64_simd_register" + (and (match_code "reg") + (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS") + (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS")))) + (define_predicate "aarch64_reg_or_zero" (and (match_code "reg,subreg,const_int") (ior (match_operand 0 "register_operand") |