[AArch64] Tighten predicates on SIMD shift intrinsics

gcc/

	* config/aarch64/aarch64-protos.h (aarch64_simd_const_bounds): Delete.
	* config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shl<mode>): Use
	new predicates.
	(aarch64_<sur>shll2_n<mode>): Likewise.
	(aarch64_<sur>shr_n<mode>): Likewise.
	(aarch64_<sur>sra_n<mode>: Likewise.
	(aarch64_<sur>s<lr>i_n<mode>): Likewise.
	(aarch64_<sur>qshl<u>_n<mode>): Likewise.
	* config/aarch64/aarch64.c (aarch64_simd_const_bounds): Delete.
	* config/aarch64/iterators.md (ve_mode): New.
	(offsetlr): Remap to infix text for use in new predicates.
	* config/aarch64/predicates.md (aarch64_simd_shift_imm_qi): New.
	(aarch64_simd_shift_imm_hi): Likewise.
	(aarch64_simd_shift_imm_si): Likewise.
	(aarch64_simd_shift_imm_di): Likewise.
	(aarch64_simd_shift_imm_offset_qi): Likewise.
	(aarch64_simd_shift_imm_offset_hi): Likewise.
	(aarch64_simd_shift_imm_offset_si): Likewise.
	(aarch64_simd_shift_imm_offset_di): Likewise.
	(aarch64_simd_shift_imm_bitsize_qi): Likewise.
	(aarch64_simd_shift_imm_bitsize_hi): Likewise.
	(aarch64_simd_shift_imm_bitsize_si): Likewise.
	(aarch64_simd_shift_imm_bitsize_di): Likewise.

gcc/testsuite/

	* gcc.target/aarch64/simd/vqshlb_1.c: New.

From-SVN: r215612

1 files changed, 53 insertions, 0 deletions

diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 8191169..d5b0b2a 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -279,3 +279,56 @@
 {
   return aarch64_const_vec_all_same_int_p (op, -1);
 })
+
+;; Predicates used by the various SIMD shift operations.  These
+;; fall in to 3 categories.
+;;   Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
+;;   Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
+;;   Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
+(define_predicate "aarch64_simd_shift_imm_qi"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
+
+(define_predicate "aarch64_simd_shift_imm_hi"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
+
+(define_predicate "aarch64_simd_shift_imm_si"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
+
+(define_predicate "aarch64_simd_shift_imm_di"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
+
+(define_predicate "aarch64_simd_shift_imm_offset_qi"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
+
+(define_predicate "aarch64_simd_shift_imm_offset_hi"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
+
+(define_predicate "aarch64_simd_shift_imm_offset_si"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
+
+(define_predicate "aarch64_simd_shift_imm_offset_di"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
+
+(define_predicate "aarch64_simd_shift_imm_bitsize_qi"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
+
+(define_predicate "aarch64_simd_shift_imm_bitsize_hi"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
+
+(define_predicate "aarch64_simd_shift_imm_bitsize_si"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
+
+(define_predicate "aarch64_simd_shift_imm_bitsize_di"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 0, 64)")))