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authorAlex Velenko <Alex.Velenko@arm.com>2014-01-23 16:24:13 +0000
committerJames Greenhalgh <jgreenhalgh@gcc.gnu.org>2014-01-23 16:24:13 +0000
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parent949ad9715a88d9010f3e6470a97b02080d500396 (diff)
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[PATCH][AArch64] Vector shift by 64 fix
gcc/ * config/aarch64/aarch64-simd-builtins.def (ashr): DI mode removed. (ashr_simd): New builtin handling DI mode. * config/aarch64/aarch64-simd.md (aarch64_ashr_simddi): New pattern. (aarch64_sshr_simddi): New match pattern. * config/aarch64/arm_neon.h (vshr_n_s32): Builtin call modified. (vshrd_n_s64): Likewise. * config/aarch64/predicates.md (aarch64_shift_imm64_di): New predicate. gcc/testsuite/ * gcc.target/aarch64/sshr64_1.c: New testcase. From-SVN: r206978
Diffstat (limited to 'gcc/config/aarch64/predicates.md')
-rw-r--r--gcc/config/aarch64/predicates.md4
1 files changed, 4 insertions, 0 deletions
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 45fcdc9..c8e27d8 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -86,6 +86,10 @@
(and (match_code "const_int")
(match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
+(define_predicate "aarch64_shift_imm64_di"
+ (and (match_code "const_int")
+ (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
+
(define_predicate "aarch64_reg_or_shift_imm_si"
(ior (match_operand 0 "register_operand")
(match_operand 0 "aarch64_shift_imm_si")))