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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2018-05-24 08:53:39 +0000 |
|---|---|---|
| committer | Andre Vieira <avieira@gcc.gnu.org> | 2018-05-24 08:53:39 +0000 |
| commit | ac025fd6cb720cd5f1a31cea7751f7206e9f767f (patch) | |
| tree | dbd76ddc29df4e2ed978b1568abe0eb8a84e7899 /gcc/config/aarch64/predicates.md | |
| parent | 5d75ad95aa808d6767afc0cdadd3b62e831c5cdf (diff) | |
| download | gcc-ac025fd6cb720cd5f1a31cea7751f7206e9f767f.zip gcc-ac025fd6cb720cd5f1a31cea7751f7206e9f767f.tar.gz gcc-ac025fd6cb720cd5f1a31cea7751f7206e9f767f.tar.bz2 | |
PR target/83009: Relax strict address checking for store pair lanes
The operand constraint for the memory address of store/load pair lanes was
enforcing strictly hardware registers be allowed as memory addresses. We want
to relax that such that these patterns can be used by combine. During register
allocation the register constraint will enforce the correct register is chosen.
gcc
2018-05-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/83009
* config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make
address check not strict.
gcc/testsuite
2018-05-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/83009
* gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests.
From-SVN: r260635
Diffstat (limited to 'gcc/config/aarch64/predicates.md')
| -rw-r--r-- | gcc/config/aarch64/predicates.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 7aec76d..4814b93 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -226,7 +226,7 @@ ;; as a 128-bit vec_concat. (define_predicate "aarch64_mem_pair_lanes_operand" (and (match_code "mem") - (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), 1, + (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), false, ADDR_QUERY_LDP_STP)"))) (define_predicate "aarch64_prefetch_operand" |