[AArch64_be] Fix vec_select hi/lo mask confusions.

gcc/

	* config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Vary
	the generated mask based on BYTES_BIG_ENDIAN.
	(aarch64_simd_check_vect_par_cnst_half): New.
	* config/aarch64/aarch64-protos.h
	(aarch64_simd_check_vect_par_cnst_half): New.
	* config/aarch64/predicates.md (vect_par_cnst_hi_half): Refactor
	the check out to aarch64_simd_check_vect_par_cnst_half.
	(vect_par_cnst_lo_half): Likewise.
	* config/aarch64/aarch64-simd.md
	(aarch64_simd_move_hi_quad_<mode>): Always use vec_par_cnst_lo_half.
	(move_hi_quad_<mode>): Always generate a low mask.

From-SVN: r213378

1 files changed, 2 insertions, 49 deletions

diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 2702a3c..95d1910 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -207,62 +207,15 @@
 (define_special_predicate "vect_par_cnst_hi_half"
   (match_code "parallel")
 {
-  HOST_WIDE_INT count = XVECLEN (op, 0);
-  int nunits = GET_MODE_NUNITS (mode);
-  int i;
-
-  if (count < 1
-      || count != nunits / 2)
-    return false;
- 
-  if (!VECTOR_MODE_P (mode))
-    return false;
-
-  for (i = 0; i < count; i++)
-   {
-     rtx elt = XVECEXP (op, 0, i);
-     int val;
-
-     if (GET_CODE (elt) != CONST_INT)
-       return false;
-
-     val = INTVAL (elt);
-     if (val != (nunits / 2) + i)
-       return false;
-   }
-  return true;
+  return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
 })
 
 (define_special_predicate "vect_par_cnst_lo_half"
   (match_code "parallel")
 {
-  HOST_WIDE_INT count = XVECLEN (op, 0);
-  int nunits = GET_MODE_NUNITS (mode);
-  int i;
-
-  if (count < 1
-      || count != nunits / 2)
-    return false;
-
-  if (!VECTOR_MODE_P (mode))
-    return false;
-
-  for (i = 0; i < count; i++)
-   {
-     rtx elt = XVECEXP (op, 0, i);
-     int val;
-
-     if (GET_CODE (elt) != CONST_INT)
-       return false;
-
-     val = INTVAL (elt);
-     if (val != i)
-       return false;
-   }
-  return true;
+  return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
 })
 
-
 (define_special_predicate "aarch64_simd_lshift_imm"
   (match_code "const_vector")
 {