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AgeCommit message (Expand)AuthorFilesLines
9 daysRemove all --varch parsingJerry Zhao1-61/+0
9 daysSwitch to Zvl/Zve parsing from isa_parser, instead of varchJerry Zhao1-1/+4
9 daysDisallow any vector, not just V, when no __int128 type is presentJerry Zhao1-1/+1
2024-06-11Improve hit rate of opcode cache to compensate for not mutating insn listAndrew Waterman1-8/+13
2024-06-11Keep potentially overlapping instructions in order at head of listAndrew Waterman1-20/+32
2024-06-11Preserve the ordering of the instruction listAndrew Waterman1-22/+2
2024-06-11triggers: implement tcontrolYenHaoChen1-0/+4
2024-05-31Avoid checking ELP before every instruction fetchAndrew Waterman1-10/+6
2024-05-31No need to check if Zicfilp is enabled before checking ELPAndrew Waterman1-3/+1
2024-04-18Add Zicfiss extension from CFI extension, v0.4.0SuHsien Ho1-3/+11
2024-03-25Narrow scontext.data length to 32YenHaoChen1-1/+1
2024-03-21Merge pull request #1582 from mylai-mtk/zicfilp-upstreamAndrew Waterman1-5/+34
2024-03-07workaround to support custom extensions that use standard prefixesAlexander Romanov1-24/+40
2024-03-06Zicfilp: Support delegating software check exception handlingMing-Yi Lai1-1/+2
2024-03-06Zicfilp: Preserve expected landing pad state on trapsMing-Yi Lai1-1/+9
2024-03-06Zicfilp: Check that the next insn is a lpad if ELP is LP_EXPECTEDMing-Yi Lai1-0/+15
2024-03-06Zicfilp: Set ELP state when executing indirect jumpsMing-Yi Lai1-0/+2
2024-03-06Zicfilp: Add CSR fieldsMing-Yi Lai1-3/+6
2024-02-06Fix hvip.VSEIP and hvip.VSTIP, so they don't observe platform-specific interr...YenHaoChen1-10/+1
2024-01-11Fix vectored VS-level interruptsScott Johnson1-1/+1
2024-01-11Introduce adjusted_cause which I will reuse nextScott Johnson1-1/+2
2024-01-11Introduce interrupt_bit which I will reuse nextScott Johnson1-1/+2
2023-12-30Add srmcfg CSRVed Shanbhogue1-1/+7
2023-12-22typo: correct sstateen CSR addressYenHaoChen1-1/+1
2023-12-08Remove cfg_arg_t from cfg_tJerry Zhao1-1/+1
2023-12-07refactor: single statement of declaration and initialization on miselect, sis...YenHaoChen1-6/+3
2023-12-06miselect: support miselect when enabling smcsrindYenHaoChen1-0/+3
2023-11-04expose pmp granularity as a cli option.Karthik B K1-1/+1
2023-08-14rename *envcfg.HADE to *envcfg.ADUEVed Shanbhogue1-2/+2
2023-07-26Add Smcntrpmf functionalityAtul Khare1-2/+21
2023-07-26Add prv_changed / v_changed fields to stateAtul Khare1-0/+4
2023-07-25Merge pull request #1383 from rivosinc/sscrind_featureAndrew Waterman1-0/+40
2023-07-25legalize menvcfg.CBIEYenHaoChen1-1/+1
2023-07-19Add Smcsrind/Sscsrind supportAtul Khare1-0/+40
2023-07-11Remove dependency of isa_parser_t on extension_tJerry Zhao1-1/+1
2023-06-19Implement Zacas extension.Gianluca Guida1-0/+5
2023-05-26Fix check for extensionGianluca Guida1-1/+1
2023-05-26Use HAVE_INT128 instead of __SIZEOF_INT128__Gianluca Guida1-1/+1
2023-05-25Refactor set_privilege to subsume set_virtAndrew Waterman1-28/+7
2023-05-25Move setting of V=0 for M-mode trapScott Johnson1-1/+1
2023-05-25Move setting of V=0 for HS-mode trapScott Johnson1-1/+1
2023-05-25Explicitly use the nonvirtual S-mode CSRs when going to HS-modeScott Johnson1-12/+12
2023-05-25Force V=1 when going to VS-mode trap handlerScott Johnson1-0/+1
2023-05-25Prevent possibility of V=1 and PRV=M when entering debug modeAndrew Waterman1-0/+1
2023-05-25Implement dcsr.v and make DRET use itAndrew Waterman1-1/+1
2023-05-24Add prev_prv to processor stateAtul Khare1-1/+2
2023-05-24Add pre_v to processor stateAtul Khare1-12/+11
2023-05-11Use passed in virtual bit for creating traps in take_trigger_action() rahter ...rbuchner1-1/+1
2023-05-11Plumb in effective virtual bit to take_trigger_action()rbuchner1-1/+1
2023-04-11explicitly show D(-mode) instead of M(-mode) when in debug modeYenHaoChen1-0/+2
generated by cgit v1.1 at 2024-06-30 11:35:34 +0000