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| author | Scott Johnson <scott.johnson@arilinc.com> | 2023-05-24 15:05:38 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-05-25 14:35:43 -0700 |
| commit | 0abf98f6f6d5b23b3d23f0c1af0b77b95a199bfe (patch) | |
| tree | 983cb8580f2e274a66980465be78e13b1ec7cdbe /riscv/processor.cc | |
| parent | 87bf9900832003ab2001158ca5d34e226e492df2 (diff) | |
| download | riscv-isa-sim-0abf98f6f6d5b23b3d23f0c1af0b77b95a199bfe.zip riscv-isa-sim-0abf98f6f6d5b23b3d23f0c1af0b77b95a199bfe.tar.gz riscv-isa-sim-0abf98f6f6d5b23b3d23f0c1af0b77b95a199bfe.tar.bz2 | |
Move setting of V=0 for M-mode trap
So it's right next to set_privilege() which it will be combined with next.
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 6fffc31..4bcf41f 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -861,7 +861,6 @@ void processor_t::take_trap(trap_t& t, reg_t epc) set_privilege(PRV_S); } else { // Handle the trap in M-mode - set_virt(false); const reg_t vector = (state.mtvec->read() & 1) && interrupt ? 4 * bit : 0; const reg_t trap_handler_address = (state.mtvec->read() & ~(reg_t)1) + vector; // RNMI exception vector is implementation-defined. Since we don't model @@ -883,6 +882,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) s = set_field(s, MSTATUS_GVA, t.has_gva()); state.mstatus->write(s); if (state.mstatush) state.mstatush->write(s >> 32); // log mstatush change + set_virt(false); set_privilege(PRV_M); } } |