diff options
| author | Scott Johnson <scott.johnson@arilinc.com> | 2023-04-27 13:19:11 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2024-01-11 17:43:17 -0800 |
| commit | 7ed22f01fc8590582d75aa46adaf76409fc198f6 (patch) | |
| tree | 7520c2af6bd9be26073baee7817d41187565829f /riscv/processor.cc | |
| parent | f80fc52e8842d3a5270b787a0fc57028edca5dab (diff) | |
| download | riscv-isa-sim-7ed22f01fc8590582d75aa46adaf76409fc198f6.zip riscv-isa-sim-7ed22f01fc8590582d75aa46adaf76409fc198f6.tar.gz riscv-isa-sim-7ed22f01fc8590582d75aa46adaf76409fc198f6.tar.bz2 | |
Introduce interrupt_bit which I will reuse next
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 3c923ea..f9c1a66 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -866,7 +866,8 @@ void processor_t::take_trap(trap_t& t, reg_t epc) reg_t vsdeleg, hsdeleg; reg_t bit = t.cause(); bool curr_virt = state.v; - bool interrupt = (bit & ((reg_t)1 << (max_xlen - 1))) != 0; + const reg_t interrupt_bit = (reg_t)1 << (max_xlen - 1); + bool interrupt = (bit & interrupt_bit) != 0; if (interrupt) { vsdeleg = (curr_virt && state.prv <= PRV_S) ? state.hideleg->read() : 0; hsdeleg = (state.prv <= PRV_S) ? state.mideleg->read() : 0; |