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author | Ming-Yi Lai <ming-yi.lai@mediatek.com> | 2024-01-10 14:22:58 +0800 |
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committer | Ming-Yi Lai <ming-yi.lai@mediatek.com> | 2024-03-06 17:21:01 +0800 |
commit | 677e030594aa51ea8d6304d24b7da2ecd7006fe8 (patch) | |
tree | 1ef9eb219ecf2f00454ce105fd1b0e107231f5a5 /riscv/processor.cc | |
parent | 7b5eba94285f1d12e8268899d3276bd0ff21d9c4 (diff) | |
download | riscv-isa-sim-677e030594aa51ea8d6304d24b7da2ecd7006fe8.zip riscv-isa-sim-677e030594aa51ea8d6304d24b7da2ecd7006fe8.tar.gz riscv-isa-sim-677e030594aa51ea8d6304d24b7da2ecd7006fe8.tar.bz2 |
Zicfilp: Support delegating software check exception handling
Diffstat (limited to 'riscv/processor.cc')
-rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 4f78879..165d7b9 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -382,7 +382,8 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) (1 << CAUSE_USER_ECALL) | (1 << CAUSE_FETCH_PAGE_FAULT) | (1 << CAUSE_LOAD_PAGE_FAULT) | - (1 << CAUSE_STORE_PAGE_FAULT); + (1 << CAUSE_STORE_PAGE_FAULT) | + (1 << CAUSE_SOFTWARE_CHECK_FAULT); csrmap[CSR_HEDELEG] = hedeleg = std::make_shared<masked_csr_t>(proc, CSR_HEDELEG, hedeleg_mask, 0); csrmap[CSR_HCOUNTEREN] = hcounteren = std::make_shared<masked_csr_t>(proc, CSR_HCOUNTEREN, counteren_mask, 0); htimedelta = std::make_shared<basic_csr_t>(proc, CSR_HTIMEDELTA, 0); |