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Suggested in https://github.com/riscv-software-src/riscv-isa-sim/pull/1816#pullrequestreview-2331806142.
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Enable more configuration using the DTB
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Avoid magic constants in hpmcounter implementation
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I introduced a regression in #1753.
Resolves #1755
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This incidentally makes it easier to support heterogeneous-hart configs
in the future
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The simplest fix is to create the CSRs even if they don't need to exist,
and just skip adding them to the CSR map to prevent the target machine
from being able to access them.
It looks like there are other place we should be following this pattern:
e.g. why does sstatus exist if S-mode does not exist? But that's a
matter for another day.
Resolves #1752
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The part is introducd by ea70a93 to keep backward compatiable but the
behavior is not mentioned and defined in spec. The patch remove this
initialization part of pbmt in [mh]envcfg
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Fix: Vector CSRs exist without any vector extension since a484f6e
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enable M -> S and HS -> VU/VS delegation
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Implement Debug spec Section 5.7.6. Trigger Control (tcontrol).
This commit lets tcontrol be read-only 0 if number of triggers is 0.
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Serialize after setting ELP. That way, we can hoist the check
outside of the main simulation loop.
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ELP will be zero if Zicfilp is not enabled.
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1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name.
2. Add new software exception with tval 3 for shadow stack.
3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d.
4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding.
5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page.
6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag.
7. Check special pte(xwr=010) of SS page.
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The commit provdes the change between debug spec 1.0.0-rc1 and 1.0.0-rc2
Reference: https://github.com/riscv/riscv-debug-spec/pull/981
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Support Zicfilp
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RISC-V ISA states (21.1):
"A standard-compatible global encoding can also use standard prefixes
for non-standard extensions if the associated standard extensions are
not included in the global encoding."
Currently all the instructions (either from standard or custom
extensions) are all being inserted into a single std::vector which is
then being sorted. An instruction matching process performs linear
search on that vector. The problem is that when a custom extension uses
the same opcode as standard one (i.e. match and mask are equal to the
standard counterparts) it is undefined which instruction will be picked.
That is because in std::sort "The order of equal elements is not
guaranteed to be preserved". That being said it is impossible to define
custom extension (via customext) that would use the prefix of a disabled
standard extension.
In this change I separate custom and standard extensions in two separate
std::vector's. By default we report an error if they have common
elements (There're an additional processor_t constructor's argument that
skips this check). If this error is disabled during instruction matching
we first trying to find it among custom instructions. If it has been
found the search is stopped and custom instruction is executed,
otherwise we look for it among standard instructions. Overall this
change does not completely fix the problem but at least makes it
possible to use the feature of RISC-V ISA.
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interrupts or CSR hgeip bits
The H extension defines that bits VSEIP, VSTIP, and VSSIP of hvip are
writable. (The other bits of hvip are read-only 0.) Only hip.VSSIP
(mip.VSSIP) is an alias of hvip.VSSIP. The hip.VSEIP is the logical-OR
of hvip.VSEIP, selected bit of hgeip by hstatus.VGEIN, and
platform-specific external interrupt signals to VS-level, e.g., from
AIA. The hip.VSTIP is the logical-OR of hvip.VSTIP and platform-specific
timer interrupt signals to VS-level, e.g., from Sstc. Thus, the read
values of hvip.VSEIP and hvip.VSTIP differ from the ones of hip.VSEIP
and hip.VSTIP (mip.VSEIP and mip.VSTIP). In other words, the hvip isn't
an alias (proxy) of mip.
The current aliasing (proxy) implementation does not provide the desired
behavior for hvip.VSEIP and hvip.VSTIP. An ISA-level behavior difference
is that any platform-specific external and timer interrupt signals
directed to VS-level should not be observable through the hvip. For
instance, the hvip should not observe the virtual timer interrupt signal
from the vstimecmp CSR (Sstc extension), which isn't true in the current
implementation. Additionally, the hvip should not observe the virtual
external interrupt signal from the IMSIC device (AIA extension).
Another ISA-level behavior difference is that the hgeip and
hstatus.VGEIN also should not affect hvip.VSEIP, which isn't true in the
current implementation.
This commit fixes the issue by giving the hvip a specialized class,
hvip_csr_t. The hvip_csr_t aliases the hvip.VSSIP to the mip.VSSIP but
decouples the hvip.VSEIP and hvip.VSTIP from mip.VSEIP and mip.VSTIP.
Additionally, the commit updates the read value of mip to be the
logical-OR of hvip.VSEIP, hvip.VSTIP, and other sources.
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They were going to the vector for cause 10 (VSEI) even though vscause
had been correctly translated to 9 (SEI).
Fixes #1340.
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Argument parsing should be scoped to the code which constucts cfg_t
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siselect, and vsiselect
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Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
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PMP Granularity is made available as a command line option. The default
value is 4 Bytes. The value can be changed by passing the option
--pmp-granularity=<value> to spike.
Signed-off-by: Karthik B K <karthik.bk@incoresemi.com>
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If Smcntrpmf is enabled, mcycle / minstret increment only if counting
for the privilege level isn't inhibited in mcyclecfg / minstretcfg.
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