diff options
| author | Scott Johnson <scott.johnson@arilinc.com> | 2023-05-24 15:05:08 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-05-25 14:35:43 -0700 |
| commit | 87bf9900832003ab2001158ca5d34e226e492df2 (patch) | |
| tree | a5eec73cbdbec14c48003f34427bc3dfbd3b2a25 /riscv/processor.cc | |
| parent | 505ddebefffed9f0e5b6dbf644719bc33adaa396 (diff) | |
| download | riscv-isa-sim-87bf9900832003ab2001158ca5d34e226e492df2.zip riscv-isa-sim-87bf9900832003ab2001158ca5d34e226e492df2.tar.gz riscv-isa-sim-87bf9900832003ab2001158ca5d34e226e492df2.tar.bz2 | |
Move setting of V=0 for HS-mode trap
So it's right next to set_privilege() which it will be combined with
next.
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index f0e8ebf..6fffc31 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -836,7 +836,6 @@ void processor_t::take_trap(trap_t& t, reg_t epc) set_privilege(PRV_S); } else if (state.prv <= PRV_S && bit < max_xlen && ((hsdeleg >> bit) & 1)) { // Handle the trap in HS-mode - set_virt(false); reg_t vector = (state.nonvirtual_stvec->read() & 1) && interrupt ? 4 * bit : 0; state.pc = (state.nonvirtual_stvec->read() & ~(reg_t)1) + vector; state.nonvirtual_scause->write(t.cause()); @@ -858,6 +857,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) s = set_field(s, HSTATUS_GVA, t.has_gva()); state.hstatus->write(s); } + set_virt(false); set_privilege(PRV_S); } else { // Handle the trap in M-mode |