aboutsummaryrefslogtreecommitdiff
path: root/riscv/processor.cc
diff options
context:
space:
mode:
authorYenHaoChen <howard25336284@gmail.com>2023-12-22 12:04:45 +0800
committerYenHaoChen <howard25336284@gmail.com>2023-12-22 12:04:45 +0800
commita80115ddf484c3b105cb5adaa7196805c1640425 (patch)
treef82410e6a8ec54a448dce6732733d779504168f4 /riscv/processor.cc
parentb98de6f689b426dce3f3d013408b4017b1018c08 (diff)
downloadriscv-isa-sim-a80115ddf484c3b105cb5adaa7196805c1640425.zip
riscv-isa-sim-a80115ddf484c3b105cb5adaa7196805c1640425.tar.gz
riscv-isa-sim-a80115ddf484c3b105cb5adaa7196805c1640425.tar.bz2
typo: correct sstateen CSR address
Diffstat (limited to 'riscv/processor.cc')
-rw-r--r--riscv/processor.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 1bb1fc9..09e8e1c 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -504,7 +504,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
}
const reg_t sstateen_mask = i == 0 ? sstateen0_mask : 0;
- csrmap[CSR_SSTATEEN0 + i] = sstateen[i] = std::make_shared<sstateen_csr_t>(proc, CSR_HSTATEEN0 + i, sstateen_mask, 0, i);
+ csrmap[CSR_SSTATEEN0 + i] = sstateen[i] = std::make_shared<sstateen_csr_t>(proc, CSR_SSTATEEN0 + i, sstateen_mask, 0, i);
}
}