Age | Commit message (Collapse) | Author | Files | Lines |
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Implement Debug spec Section 5.7.6. Trigger Control (tcontrol).
This commit lets tcontrol be read-only 0 if number of triggers is 0.
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Serialize after setting ELP. That way, we can hoist the check
outside of the main simulation loop.
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Based on Spec chapter 3.5
"An MRET or SRET instruction is used to return from a trap in M-mode or
S-mode, respectively. When executing an xRET instruction, if xPP holds
the value y, then ELP is set to the value of xPELP if yLPE is 1;
otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED."
The change follow the last statement after semicolon
"xPELP is set to NO_LP_EXPECTED"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name.
2. Add new software exception with tval 3 for shadow stack.
3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d.
4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding.
5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page.
6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag.
7. Check special pte(xwr=010) of SS page.
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Support Zicfilp
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Vmcompress.vm requires vstart==0, so writing vstart with 0 is redundant.
To do this, spin off VI_LOOP_END_BASE from VI_LOOP_END. VI_LOOP_END
will contain VI_LOOP_END_BASE as well as a write of 0 to vstart.
See #1623 for full discussion.
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Fix c.mop.N decoding
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VU-mode
The previous implementation raises virtual instruction on WFI when TW=1 in VU-mode. According to the recent discussion, we expect an illegal instruction exception in this case.
Reference: https://github.com/riscv/riscv-isa-manual/issues/1234
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The c.mop.N only accepts rd={x1, x3, x5, x7, x9, x11, x13, x15}. The
previous implemention incorrectly accepts additional rd={x17, x19, x21,
x23, x25, x27, x29, x31}.
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zip and unzip of Zbkb require RV32
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Signed-off-by: demin.han <demin.han@starfivetech.com>
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1. put_csr needs search
2. MSTATUS_MPV not written back for RV32
Signed-off-by: demin.han <demin.han@starfivetech.com>
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Signed-off-by: Madman <1017747824@qq.com>
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Resolves #1507
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: viktoryou <143797577+viktoryou@users.noreply.github.com>
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Implement the Zvksh sub-extension, "ShangMi Suite: SM3 Hash
Function Instructions":
- vsm3me.vv, message expansion,
- vsm3c.vi, compression rounds.
This also introduces a SM3 specific header for common logic.
Co-authored-by: Raghav Gupta <rgupta@rivosinc.com>
Co-authored-by: Albert Jakieła <aja@semihalf.com>
Co-authored-by: Kornel Dulęba <mindal@semihalf.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
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Implement the Zvksed sub-extension, "ShangMi Suite: SM4 Block Cipher":
- vsm4k.vi, vector SM4 key expansion,
- vsm4r.{vs,vv}, vector SM4 rounds.
This also introduces a header for common vector SM4 logic.
Co-authored-by: Raghav Gupta <rgupta@rivosinc.com>
Co-authored-by: Albert Jakieła <aja@semihalf.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
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Implement the Zvkned extension, "NIST Suite: Vector AES Encryption
& Decryption (Single Round)".
- vaeskf1.vi: AES forward key scheduling, AES-128.
- vaeskf2.vi: AES forward key scheduling, AES-256.
- vaesz.vs: AES encryption/decryption, 0-th round.
- vaesdm.{vs,vv}: AES decryption, middle rounds.
- vaesdf.{vs,vv}: AES decryption, final round.
- vaesem.{vs,vv}: AES encryption, middle rounds.
- vaesef.{vs,vv}: AES encryption, final round.
An extension specific header containing common logic is added.
Co-authored-by: Stanislaw Kardach <kda@semihalf.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
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Implement the instructions part of the Zvknha and Zvknhb
sub-extensions:
- vsha2ms.vv, message schedule
- vsha2ch.vv / vsha2cl.vv, compression rounds
A header files for common macros is added.
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
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Implement the proposed instruction in Zvkg, vghmac.vv,
Vector Carryless Multiply Accumulate over GHASH Galois-Field.
The instruction performs one step of GHASH routine as described
in "NIST Special Publication 800-38D" a.k.a the AES-GCM specification.
The logic was written to closely track the pseudo-code
in the Zvk specification.
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
Co-authored-by: Kornel Duleba <mindal@semihalf.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
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Implement the Zvbc instructions
- vclmul.{vv,vx}, vector carryless multiply low
- vclmulh.{vv,vx}, vector carryless multiply high
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
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Implement the proposed instructions in Zvbb:
- vandn.{vv,vx}, vector bitwise and-not
- vbrev.v, vector bit reverse in element
- vbrev8.v, vector bit reverse in bytes
- vrev8.v, vector byte reverse
- vctz.v, vector count trailing zeros
- vclz.v, vector count leading zeros
- vcpop.v, vector population count
- vrol.{vv,vx}, vector rotate left
- vror.{vi,vv,vx}, vector rotate right
- vwsll.{vi,vv,vx} vector widening shift left logical
A new instruction field, 'zimm6', is introduced, encoded
in bits [15, 19] and [26].. It is used by "vror.vi" to encode
a shift immediate in [0, 63].
Co-authored-by: Raghav Gupta <rgupta@rivosinc.com>
Co-authored-by: Stanislaw Kardach <kda@semihalf.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
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Add support for BF16 extensions
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This change was made ages ago in the spec.
I did not actually test that the new privilege checks in ebreak and
c.ebreak are correct, but all the existing debug tests still pass.
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This cleans up the code and avoids bugs like #1365.
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Resolves #1365
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