Merge pull request #1321 from plctlab/plct-bf16-dev

Add support for BF16 extensions

10 files changed, 34 insertions, 4 deletions

diff --git a/riscv/insns/fcvt_bf16_s.h b/riscv/insns/fcvt_bf16_s.h
new file mode 100644
index 0000000..d625df8
--- /dev/null
+++ b/riscv/insns/fcvt_bf16_s.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFBFMIN);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD_BF(f32_to_bf16(FRS1_F));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_bf16.h b/riscv/insns/fcvt_s_bf16.h
new file mode 100644
index 0000000..59a55cb
--- /dev/null
+++ b/riscv/insns/fcvt_s_bf16.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFBFMIN);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD_F(bf16_to_f32(FRS1_BF));
+set_fp_exceptions;
diff --git a/riscv/insns/flh.h b/riscv/insns/flh.h
index befff2c..67b538a 100644
--- a/riscv/insns/flh.h
+++ b/riscv/insns/flh.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFHMIN);
+require_extension(EXT_INTERNAL_ZFH_MOVE);
 require_fp;
 WRITE_FRD(f16(MMU.load<uint16_t>(RS1 + insn.i_imm())));
diff --git a/riscv/insns/fmv_h_x.h b/riscv/insns/fmv_h_x.h
index e55d607..bc2155c 100644
--- a/riscv/insns/fmv_h_x.h
+++ b/riscv/insns/fmv_h_x.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFHMIN);
+require_extension(EXT_INTERNAL_ZFH_MOVE);
 require_fp;
 WRITE_FRD(f16(RS1));
diff --git a/riscv/insns/fmv_x_h.h b/riscv/insns/fmv_x_h.h
index 7a2e5ff..ca823c1 100644
--- a/riscv/insns/fmv_x_h.h
+++ b/riscv/insns/fmv_x_h.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFHMIN);
+require_extension(EXT_INTERNAL_ZFH_MOVE);
 require_fp;
 WRITE_RD(sext32((int16_t)(FRS1.v[0])));
diff --git a/riscv/insns/fsh.h b/riscv/insns/fsh.h
index dfd6bc5..142d4d4 100644
--- a/riscv/insns/fsh.h
+++ b/riscv/insns/fsh.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFHMIN);
+require_extension(EXT_INTERNAL_ZFH_MOVE);
 require_fp;
 MMU.store<uint16_t>(RS1 + insn.s_imm(), FRS2.v[0]);
diff --git a/riscv/insns/vfncvtbf16_f_f_w.h b/riscv/insns/vfncvtbf16_f_f_w.h
new file mode 100644
index 0000000..4708802
--- /dev/null
+++ b/riscv/insns/vfncvtbf16_f_f_w.h
@@ -0,0 +1,5 @@
+// vfncvtbf16.f.f.w vd, vs2, vm
+VI_VFP_NCVT_BF16_TO_FP(
+  { vd = f32_to_bf16(vs2); },           // BODY16
+  { require_extension(EXT_ZVFBFMIN); }  // CHECK16
+)
diff --git a/riscv/insns/vfwcvtbf16_f_f_v.h b/riscv/insns/vfwcvtbf16_f_f_v.h
new file mode 100644
index 0000000..ee9a59c
--- /dev/null
+++ b/riscv/insns/vfwcvtbf16_f_f_v.h
@@ -0,0 +1,5 @@
+// vfwcvtbf16.f.f.v vd, vs2, vm
+VI_VFP_WCVT_FP_TO_BF16(
+  { vd = bf16_to_f32(vs2); },           // BODY16
+  { require_extension(EXT_ZVFBFMIN); }  // CHECK16
+)
diff --git a/riscv/insns/vfwmaccbf16_vf.h b/riscv/insns/vfwmaccbf16_vf.h
new file mode 100644
index 0000000..2c77b3b
--- /dev/null
+++ b/riscv/insns/vfwmaccbf16_vf.h
@@ -0,0 +1,5 @@
+// vfwmaccbf16.vf vd, vs2, rs1
+VI_VFP_BF16_VF_LOOP_WIDE
+({
+  vd = f32_mulAdd(rs1, vs2, vd);
+})
diff --git a/riscv/insns/vfwmaccbf16_vv.h b/riscv/insns/vfwmaccbf16_vv.h
new file mode 100644
index 0000000..bd8f305
--- /dev/null
+++ b/riscv/insns/vfwmaccbf16_vv.h
@@ -0,0 +1,5 @@
+// vfwmaccbf16.vv vd, vs2, vs1
+VI_VFP_BF16_VV_LOOP_WIDE
+({
+  vd = f32_mulAdd(vs1, vs2, vd);
+})