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author | YenHaoChen <howard25336284@gmail.com> | 2024-02-19 13:09:12 +0800 |
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committer | YenHaoChen <howard25336284@gmail.com> | 2024-02-19 16:41:27 +0800 |
commit | 4a2b38ffcf8dd01320f601d6014464f510904e53 (patch) | |
tree | fe72b4a8bcf326a5edce3cc2e0400dc8fff76c0b /riscv/insns | |
parent | 7c890632ec91104fe6ccd9f16f70842c4412a1fd (diff) | |
download | riscv-isa-sim-4a2b38ffcf8dd01320f601d6014464f510904e53.zip riscv-isa-sim-4a2b38ffcf8dd01320f601d6014464f510904e53.tar.gz riscv-isa-sim-4a2b38ffcf8dd01320f601d6014464f510904e53.tar.bz2 |
Raise illegal instruction instead of virtual instruction on WFI when TW=1 in VU-mode
The previous implementation raises virtual instruction on WFI when TW=1 in VU-mode. According to the recent discussion, we expect an illegal instruction exception in this case.
Reference: https://github.com/riscv/riscv-isa-manual/issues/1234
Diffstat (limited to 'riscv/insns')
-rw-r--r-- | riscv/insns/wfi.h | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/riscv/insns/wfi.h b/riscv/insns/wfi.h index 3411da0..5382072 100644 --- a/riscv/insns/wfi.h +++ b/riscv/insns/wfi.h @@ -1,9 +1,7 @@ -if (STATE.v && STATE.prv == PRV_U) { - require_novirt(); -} else if (get_field(STATE.mstatus->read(), MSTATUS_TW)) { +if (get_field(STATE.mstatus->read(), MSTATUS_TW)) { require_privilege(PRV_M); -} else if (STATE.v) { // VS-mode - if (get_field(STATE.hstatus->read(), HSTATUS_VTW)) +} else if (STATE.v) { + if (STATE.prv == PRV_U || get_field(STATE.hstatus->read(), HSTATUS_VTW)) require_novirt(); } else if (p->extension_enabled('S')) { // When S-mode is implemented, then executing WFI in |