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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-14 22:49:24 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-05-29 09:01:21 +0800 |
| commit | 48f66191758f3bca04e6d7e85348f266df148c14 (patch) | |
| tree | 0fb6548e20dbb276210b1515d232bcd7fa5eebe0 /riscv/insns | |
| parent | 8aacc4effde92122a25beadac594162187767d7e (diff) | |
| download | riscv-isa-sim-48f66191758f3bca04e6d7e85348f266df148c14.zip riscv-isa-sim-48f66191758f3bca04e6d7e85348f266df148c14.tar.gz riscv-isa-sim-48f66191758f3bca04e6d7e85348f266df148c14.tar.bz2 | |
Add support for new instructions of Zvfbfwma extension
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/vfwmaccbf16_vf.h | 5 | ||||
| -rw-r--r-- | riscv/insns/vfwmaccbf16_vv.h | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/riscv/insns/vfwmaccbf16_vf.h b/riscv/insns/vfwmaccbf16_vf.h new file mode 100644 index 0000000..2c77b3b --- /dev/null +++ b/riscv/insns/vfwmaccbf16_vf.h @@ -0,0 +1,5 @@ +// vfwmaccbf16.vf vd, vs2, rs1 +VI_VFP_BF16_VF_LOOP_WIDE +({ + vd = f32_mulAdd(rs1, vs2, vd); +}) diff --git a/riscv/insns/vfwmaccbf16_vv.h b/riscv/insns/vfwmaccbf16_vv.h new file mode 100644 index 0000000..bd8f305 --- /dev/null +++ b/riscv/insns/vfwmaccbf16_vv.h @@ -0,0 +1,5 @@ +// vfwmaccbf16.vv vd, vs2, vs1 +VI_VFP_BF16_VV_LOOP_WIDE +({ + vd = f32_mulAdd(vs1, vs2, vd); +}) |