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author | SuHsien Ho <su-hsien.ho@mediatek.com> | 2023-10-04 15:00:49 +0800 |
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committer | SuHsien Ho <su-hsien.ho@mediatek.com> | 2024-04-18 13:05:28 +0800 |
commit | 9ba5bd3171e97560bc28fe555ff7b8404272a3bb (patch) | |
tree | c0ac867c7df2ce90c83071e93c0ea5f0c6745d70 /riscv/insns | |
parent | 3192ee4d31f481e84281a24d55bb6130e3743668 (diff) | |
download | riscv-isa-sim-9ba5bd3171e97560bc28fe555ff7b8404272a3bb.zip riscv-isa-sim-9ba5bd3171e97560bc28fe555ff7b8404272a3bb.tar.gz riscv-isa-sim-9ba5bd3171e97560bc28fe555ff7b8404272a3bb.tar.bz2 |
Add Zicfiss extension from CFI extension, v0.4.0
1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name.
2. Add new software exception with tval 3 for shadow stack.
3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d.
4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding.
5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page.
6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag.
7. Check special pte(xwr=010) of SS page.
Diffstat (limited to 'riscv/insns')
-rw-r--r-- | riscv/insns/c_lui.h | 8 | ||||
-rw-r--r-- | riscv/insns/c_sspopchk_x5.h | 5 | ||||
-rw-r--r-- | riscv/insns/c_sspush_x1.h | 5 | ||||
-rw-r--r-- | riscv/insns/ssamoswap_d.h | 7 | ||||
-rw-r--r-- | riscv/insns/ssamoswap_w.h | 7 | ||||
-rw-r--r-- | riscv/insns/sspopchk_x1.h | 7 | ||||
-rw-r--r-- | riscv/insns/sspopchk_x5.h | 1 | ||||
-rw-r--r-- | riscv/insns/sspush_x1.h | 7 | ||||
-rw-r--r-- | riscv/insns/sspush_x5.h | 1 | ||||
-rw-r--r-- | riscv/insns/ssrdp.h | 7 |
10 files changed, 54 insertions, 1 deletions
diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h index 7a82c13..98a8898 100644 --- a/riscv/insns/c_lui.h +++ b/riscv/insns/c_lui.h @@ -5,7 +5,13 @@ if (insn.rvc_rd() == 2) { // c.addi16sp } else if (insn.rvc_imm() != 0) { // c.lui WRITE_RD(insn.rvc_imm() << 12); } else if ((insn.rvc_rd() & 0x11) == 1) { // c.mop.N - #include "c_mop_N.h" + if (insn.rvc_rd() == 5 && p->extension_enabled(EXT_ZICFISS)) { + #include "c_sspopchk_x5.h" + } else if (insn.rvc_rd() == 1 && p->extension_enabled(EXT_ZICFISS)) { + #include "c_sspush_x1.h" + } else { + #include "c_mop_N.h" + } } else { require(false); } diff --git a/riscv/insns/c_sspopchk_x5.h b/riscv/insns/c_sspopchk_x5.h new file mode 100644 index 0000000..d379f2c --- /dev/null +++ b/riscv/insns/c_sspopchk_x5.h @@ -0,0 +1,5 @@ +#include "zicfiss.h" + +if (xSSE()) { + POP_VALUE_FROM_SS_AND_CHECK(READ_REG(X_T0)); +} diff --git a/riscv/insns/c_sspush_x1.h b/riscv/insns/c_sspush_x1.h new file mode 100644 index 0000000..3645a9e --- /dev/null +++ b/riscv/insns/c_sspush_x1.h @@ -0,0 +1,5 @@ +#include "zicfiss.h" + +if (xSSE()) { + PUSH_VALUE_TO_SS(RA); +} diff --git a/riscv/insns/ssamoswap_d.h b/riscv/insns/ssamoswap_d.h new file mode 100644 index 0000000..10ea5ef --- /dev/null +++ b/riscv/insns/ssamoswap_d.h @@ -0,0 +1,7 @@ +require_extension(EXT_ZICFISS); +require_extension('A'); +require_rv64; + +DECLARE_XENVCFG_VARS(SSE); +require_envcfg(SSE); +WRITE_RD(MMU.ssamoswap<uint64_t>(RS1, RS2)); diff --git a/riscv/insns/ssamoswap_w.h b/riscv/insns/ssamoswap_w.h new file mode 100644 index 0000000..3cdefc7 --- /dev/null +++ b/riscv/insns/ssamoswap_w.h @@ -0,0 +1,7 @@ +require_extension(EXT_ZICFISS); +require_extension('A'); + +DECLARE_XENVCFG_VARS(SSE); +require_envcfg(SSE); +WRITE_RD(sext32(MMU.ssamoswap<uint32_t>(RS1, RS2))); + diff --git a/riscv/insns/sspopchk_x1.h b/riscv/insns/sspopchk_x1.h new file mode 100644 index 0000000..6ea4c22 --- /dev/null +++ b/riscv/insns/sspopchk_x1.h @@ -0,0 +1,7 @@ +#include "zicfiss.h" + +if (xSSE()) { + POP_VALUE_FROM_SS_AND_CHECK(RS1); +} else { + #include "mop_r_N.h" +} diff --git a/riscv/insns/sspopchk_x5.h b/riscv/insns/sspopchk_x5.h new file mode 100644 index 0000000..78218b3 --- /dev/null +++ b/riscv/insns/sspopchk_x5.h @@ -0,0 +1 @@ +#include "sspopchk_x1.h" diff --git a/riscv/insns/sspush_x1.h b/riscv/insns/sspush_x1.h new file mode 100644 index 0000000..67ad9bb --- /dev/null +++ b/riscv/insns/sspush_x1.h @@ -0,0 +1,7 @@ +#include "zicfiss.h" + +if (xSSE()) { + PUSH_VALUE_TO_SS(RS2); +} else { + #include "mop_rr_N.h" +} diff --git a/riscv/insns/sspush_x5.h b/riscv/insns/sspush_x5.h new file mode 100644 index 0000000..235333d --- /dev/null +++ b/riscv/insns/sspush_x5.h @@ -0,0 +1 @@ +#include "sspush_x1.h" diff --git a/riscv/insns/ssrdp.h b/riscv/insns/ssrdp.h new file mode 100644 index 0000000..20b0856 --- /dev/null +++ b/riscv/insns/ssrdp.h @@ -0,0 +1,7 @@ +#include "zicfiss.h" + +if (xSSE()) { + WRITE_RD(STATE.ssp->read()); +} else { + #include "mop_r_N.h" +} |