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author | Eric Gouriou <ego@rivosinc.com> | 2023-06-01 18:07:04 -0700 |
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committer | Eric Gouriou <ego@rivosinc.com> | 2023-06-19 14:30:34 -0700 |
commit | d633af2b180391b6f73f84f56d8b305a3af7c152 (patch) | |
tree | dfa8e1f14de06e3297ac8e357dc7fa2bd1bef3e5 /riscv/insns | |
parent | e87038ee5e6545a5149cdf4334d220f951534f30 (diff) | |
download | riscv-isa-sim-d633af2b180391b6f73f84f56d8b305a3af7c152.zip riscv-isa-sim-d633af2b180391b6f73f84f56d8b305a3af7c152.tar.gz riscv-isa-sim-d633af2b180391b6f73f84f56d8b305a3af7c152.tar.bz2 |
Zvk: Implement Zvbc extension, vectory carryless multiplaction
Implement the Zvbc instructions
- vclmul.{vv,vx}, vector carryless multiply low
- vclmulh.{vv,vx}, vector carryless multiply high
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
Diffstat (limited to 'riscv/insns')
-rw-r--r-- | riscv/insns/vclmul_vv.h | 20 | ||||
-rw-r--r-- | riscv/insns/vclmul_vx.h | 20 | ||||
-rw-r--r-- | riscv/insns/vclmulh_vv.h | 20 | ||||
-rw-r--r-- | riscv/insns/vclmulh_vx.h | 20 |
4 files changed, 80 insertions, 0 deletions
diff --git a/riscv/insns/vclmul_vv.h b/riscv/insns/vclmul_vv.h new file mode 100644 index 0000000..8957738 --- /dev/null +++ b/riscv/insns/vclmul_vv.h @@ -0,0 +1,20 @@ +// vclmul.vv vd, vs2, vs1, vm + +#include "zvk_ext_macros.h" + +require_zvbc; +require(P.VU.vsew == 64); + +VI_VV_ULOOP +({ + // Perform a carryless multiplication 64bx64b on each 64b element, + // return the low 64b of the 128b product. + // <https://en.wikipedia.org/wiki/Carry-less_product> + vd = 0; + for (std::size_t bit_idx = 0; bit_idx < sew; ++bit_idx) { + const reg_t mask = ((reg_t) 1) << bit_idx; + if ((vs1 & mask) != 0) { + vd ^= vs2 << bit_idx; + } + } +}) diff --git a/riscv/insns/vclmul_vx.h b/riscv/insns/vclmul_vx.h new file mode 100644 index 0000000..1df7a3a --- /dev/null +++ b/riscv/insns/vclmul_vx.h @@ -0,0 +1,20 @@ +// vclmul.vx vd, vs2, rs1, vm + +#include "zvk_ext_macros.h" + +require_zvbc; +require(P.VU.vsew == 64); + +VI_VX_ULOOP +({ + // Perform a carryless multiplication 64bx64b on each 64b element, + // return the low 64b of the 128b product. + // <https://en.wikipedia.org/wiki/Carry-less_product> + vd = 0; + for (std::size_t bit_idx = 0; bit_idx < sew; ++bit_idx) { + const reg_t mask = ((reg_t) 1) << bit_idx; + if ((rs1 & mask) != 0) { + vd ^= vs2 << bit_idx; + } + } +}) diff --git a/riscv/insns/vclmulh_vv.h b/riscv/insns/vclmulh_vv.h new file mode 100644 index 0000000..6a54bcf --- /dev/null +++ b/riscv/insns/vclmulh_vv.h @@ -0,0 +1,20 @@ +// vclmulh.vv vd, vs2, vs1, vm + +#include "zvk_ext_macros.h" + +require_zvbc; +require(P.VU.vsew == 64); + +VI_VV_ULOOP +({ + // Perform a carryless multiplication 64bx64b on each 64b element, + // return the high 64b of the 128b product. + // <https://en.wikipedia.org/wiki/Carry-less_product> + vd = 0; + for (std::size_t bit_idx = 1; bit_idx < sew; ++bit_idx) { + const reg_t mask = ((reg_t) 1) << bit_idx; + if ((vs1 & mask) != 0) { + vd ^= ((reg_t)vs2) >> (sew - bit_idx); + } + } +}) diff --git a/riscv/insns/vclmulh_vx.h b/riscv/insns/vclmulh_vx.h new file mode 100644 index 0000000..e874d1d --- /dev/null +++ b/riscv/insns/vclmulh_vx.h @@ -0,0 +1,20 @@ +// vclmulh.vx vd, vs2, rs1, vm + +#include "zvk_ext_macros.h" + +require_zvbc; +require(P.VU.vsew == 64); + +VI_VX_ULOOP +({ + // Perform a carryless multiplication 64bx64b on each 64b element, + // return the high 64b of the 128b product. + // <https://en.wikipedia.org/wiki/Carry-less_product> + vd = 0; + for (std::size_t bit_idx = 1; bit_idx < sew; ++bit_idx) { + const reg_t mask = ((reg_t) 1) << bit_idx; + if ((rs1 & mask) != 0) { + vd ^= ((reg_t)vs2) >> (sew - bit_idx); + } + } +}) |