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| author | Andrew Waterman <andrew@sifive.com> | 2023-05-24 13:51:34 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-05-25 14:35:42 -0700 |
| commit | d99efb545cca366a159dc1dedcbbd08fa2b3b8cf (patch) | |
| tree | 56933e75e6963c14080a179315b48ac0ca6895e4 /riscv/insns | |
| parent | e910707051c4e10889f58229443bf9d41652ed7b (diff) | |
| download | riscv-isa-sim-d99efb545cca366a159dc1dedcbbd08fa2b3b8cf.zip riscv-isa-sim-d99efb545cca366a159dc1dedcbbd08fa2b3b8cf.tar.gz riscv-isa-sim-d99efb545cca366a159dc1dedcbbd08fa2b3b8cf.tar.bz2 | |
Implement dcsr.v and make DRET use it
Resolves #1365
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/dret.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h index 56ce25b..0540c51 100644 --- a/riscv/insns/dret.h +++ b/riscv/insns/dret.h @@ -1,6 +1,7 @@ require(STATE.debug_mode); set_pc_and_serialize(STATE.dpc->read()); p->set_privilege(STATE.dcsr->prv); +p->set_virt(STATE.dcsr->v); if (STATE.prv < PRV_M) STATE.mstatus->write(STATE.mstatus->read() & ~MSTATUS_MPRV); |