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| author | Andrew Waterman <andrew@sifive.com> | 2024-05-31 01:24:02 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-05-31 01:24:02 -0700 |
| commit | 759599553bab6c95399253ba366a0f5b1b3dd48f (patch) | |
| tree | 8f84650d9d8c783ee582c8d2956cce995fd8dca1 /riscv/insns | |
| parent | 148e6d63e036a611537f7afbee771d9b83d348fb (diff) | |
| download | riscv-isa-sim-759599553bab6c95399253ba366a0f5b1b3dd48f.zip riscv-isa-sim-759599553bab6c95399253ba366a0f5b1b3dd48f.tar.gz riscv-isa-sim-759599553bab6c95399253ba366a0f5b1b3dd48f.tar.bz2 | |
Avoid checking ELP before every instruction fetch
Serialize after setting ELP. That way, we can hoist the check
outside of the main simulation loop.
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/c_jalr.h | 1 | ||||
| -rw-r--r-- | riscv/insns/c_jr.h | 1 | ||||
| -rw-r--r-- | riscv/insns/jalr.h | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/riscv/insns/c_jalr.h b/riscv/insns/c_jalr.h index 12bc7f9..694f183 100644 --- a/riscv/insns/c_jalr.h +++ b/riscv/insns/c_jalr.h @@ -6,4 +6,5 @@ WRITE_REG(X_RA, tmp); if (ZICFILP_xLPE(STATE.v, STATE.prv)) { STATE.elp = ZICFILP_IS_LP_EXPECTED(insn.rvc_rs1()); + serialize(); } diff --git a/riscv/insns/c_jr.h b/riscv/insns/c_jr.h index c5162e9..af43dd3 100644 --- a/riscv/insns/c_jr.h +++ b/riscv/insns/c_jr.h @@ -4,4 +4,5 @@ set_pc(RVC_RS1 & ~reg_t(1)); if (ZICFILP_xLPE(STATE.v, STATE.prv)) { STATE.elp = ZICFILP_IS_LP_EXPECTED(insn.rvc_rs1()); + serialize(); } diff --git a/riscv/insns/jalr.h b/riscv/insns/jalr.h index 0622a22..0606f67 100644 --- a/riscv/insns/jalr.h +++ b/riscv/insns/jalr.h @@ -4,4 +4,5 @@ WRITE_RD(tmp); if (ZICFILP_xLPE(STATE.v, STATE.prv)) { STATE.elp = ZICFILP_IS_LP_EXPECTED(insn.rs1()); + serialize(); } |