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2020-05-13rvv: fractional_lmul when lmul < 1Dave.Wen1-0/+1
2020-05-07rvv: add eew and lmul for vle/vse/vleffDave.Wen1-0/+3
2020-05-06fractional_lmul: update the vtype register and alos remove the useless reg_maskDave.Wen1-1/+3
2020-04-14parser: extend --isa to support extended extensionChih-Min Chao1-2/+15
1. support extened extension ex: --isa="imadc_zvamo_zvqmac 2. relax extenion character order --isa=imadc or --isa==cdima 3. use another bit structure to keep all supported extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-05Write execution logs to a named log file (#409)Rupert Swarbrick1-3/+9
This patch adds a --log argument to spike. If not given, the behaviour is unchanged: messages logging execution of instructions and (if commit logging is enabled) commits go to stderr. If --log=P is given, Spike now writes these messages to a log file at the path P. This is nice, because they are no longer tangled up with other errors and warnings. The code is mostly plumbing: passing a FILE* object through to the functions that were using stderr. I've written a simple "log_file_t" class, which opens a log file if necessary and yields it or stderr.
2020-03-05rvv: avoid redundant std::string comparisonZhen Wei1-1/+8
2020-03-05rvv: import parallel vf(w)redsum hardware impl.Zhen Wei1-0/+3
The number of vector FP ALUs and implementations of vf(w)redsum could be passed as options by the following example: "--varch=vlen:512,elen:32,slen:512,nalu:4,fredsum-impl:parallel" By default, 4 of vector FP ALUs and ordered vector FP reduction sum implementations are assumed.
2020-03-04rvv: remove the option of vector impl. checkZhen Wei1-4/+3
The check is not needed anymore since most vector kernels are supported in current implemented vector instruction set.
2020-02-12rvv: remove duplicate vectorUnit declarationChih-Min Chao1-58/+3
forget to remove the vectorUnit outside, which has been moved into proccess_t as inner class Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-12debug: refine per-inst difference recordChih-Min Chao1-8/+10
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-12commitlog: rvv: change vector register read/write interfaceChih-Min Chao1-0/+59
1. add an extra argument to support commitlog 2. move vectorUnit_t into processor_t to avoid circular dependency hell Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-12commitlog: extend reg record to keep multiple accesssChih-Min Chao1-5/+3
1. use hash to keep duplicated register write since vector has lmul feature 2. enhance print fuction to support type larger than 64bit Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-12commitlog: extend load/store record to keep multiple accessChih-Min Chao1-6/+2
use vector to store memory accesses Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-12-19extend the commit and memory writes log feature with memory reads (#370)John Ingalls1-0/+1
2019-11-27rvv: change vsetvl[i] to match 0.8 specChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: add read-only vleb csrChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-17Add --priv option to control which privilege modes are availableAndrew Waterman1-4/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: remove tail-zeroChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-29Implement support for big-endian hostsMarcus Comstedt1-0/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-15rvv: add new rs1 = zero feature to vsetvlChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-08Fixed match trigger MATCH_NAPOT case. (#335)fborisovskii1-1/+1
Mask calculation was not in consistency with debug spec. Watch debug spec. 5.2.7 match field overview and debug spec. B.9 fourth example. Mask should not cover LSB zero bit. Also there is a way to make it simplier: reg_t mask = ~(((~state.tdata2[i]) - 1) ^ ~state.tdata2[i]);
2019-09-29Extends the commit log feature with memory writes. (#324)dave-estes-syzexion1-0/+8
* Extends the commit log feature with memory writes. This provides a little more information for debugging instruction traces, allowing you to maintain the state of memory as the trace is processed. The following sample trace output illustrates the formatting of the new memory writes. The first line is an instruction at location 0x80000094, containing the bytes (0x80830313) and commiting the value 0x80000898 to the register x6. The second line is an instruction which neither commits a register nor writes memory. The third line writes the value 0x0 to 0x80000890. 3 0x80000094 (0x80830313) x 6 0x80000898 3 0x80000098 (0x0062d663) 3 0x8000009c (0x00028023) mem 0x80000890 0x0 * Changes addressing feedback from review.
2019-09-29Adds --log-commits commandline option. (#323)dave-estes-syzexion1-0/+3
* Adds --log-commits commandline option. Similar to histogram support, the commit logging feature must be enabled with a configure option: --enable-commitlog. However, unlike that feature, there was no way to turn off the logging with a commandline option once the functionality was built in. This (git) commit provides that abilty. * Changes addressing review feedback.
2019-09-25rvv:add t0/t1 to configure to setup default tailzero modeChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-09-04rvv: add impl_table for instruction release checkChih-Min Chao1-3/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-07-22Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome1-1/+1
* Don't corrupt s0 when abstract CSR write fails. * Support abstract FPR access then mstatus.FS=0 Discussion on the spec list leans towards this being a requirement. Certainly users want their debugger to be able to access all registers regardless of target state.
2019-07-22Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-2/+4
In the previous scheme, debug-mode software could exit debug mode by zeroing the dcsr.cause field. While benign, that behavior is out of spec.
2019-06-12rvv: merge the vcsr to ordinary csr and remove the redundant functionsDave.Wen1-2/+0
2019-06-12WIP: move from gamma07 to gamma03Dave.Wen1-1/+2
2019-06-06rvv: remove old register boundary checkingChih-Min Chao1-5/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-06rvv: remove trailing spaceChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-04rvv: refine the code for checking the varch option setDave.Wen1-3/+0
2019-04-30rvv: fixed type and removed redundant variableDave.Wen1-2/+2
2019-04-30rvv: decouple the vectorUnit to the processor's state.Dave.Wen1-61/+67
2019-04-25rvv: fix vsmulv[vx]Dave.Wen1-3/+1
2019-04-22fixed type RUN to RNUDave.Wen1-1/+1
2019-04-20improve the vectorUint_tDave1-5/+8
1. for vill, we need to know the XLEN from VU. So we put a pointer to processor in vectorUnit_t 2. add vill 3. fitting the naming convention for setVL
2019-04-15Revert "Revert "rvv: restore reg_reference keeping""Chih-Min Chao1-0/+3
revert wrong revert This reverts commit ffda9507ae644cc7700608b12d3facd2849e4cad.
2019-04-15Revert "rvv: restore reg_reference keeping"Chih-Min Chao1-3/+0
This reverts commit 085310bf0a14ca66cffeb73c4fa37fea2be2fe6c.
2019-04-15rvv: restore reg_reference keepingChih-Min Chao1-0/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-04-10rvv: simplify register offset calculationChih-Min Chao1-3/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-04-07rvv: add unsigned sew typeDave.Wen1-0/+28
2019-03-31rvv: rewrite the vector destination for varies sewDave.Wen1-0/+27
2019-03-29processor: for rounding mode and config access functionsDave.Wen1-0/+21
2019-03-28vsetvli: if rs1 = x0, then use maximum vector lengthDave.Wen1-1/+1
2019-03-27rvv: add mlen for convenientChih-Min Chao1-1/+1
mlen is the bit lenght of one element in V0 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-03-27reshape the eltDave.Wen1-5/+8
2019-03-27add vmul, sbc, and shift instructions.Dave.Wen1-2/+2
2019-02-24Add comparison of user state (XPR, FPR, VPR) after each instructionBruce Hoult1-3/+20
2019-02-08move vectorUnit_t::reset() and setVL() impl out of headerBruce Hoult1-24/+2
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